From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 38FB2385DC2D; Tue, 14 Apr 2020 14:42:48 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 38FB2385DC2D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1586875368; bh=c8MfHf7KlW7WWap41Qj5Wx1fua8p4o4sKxcQZvYuCGo=; h=From:To:Subject:Date:In-Reply-To:References:From; b=KSP0eicjkGvsEQ8OVPq+mBzaT29at8A4IkUHjUyOKmvPiLR/lyiYFWR3M8Agw5J6t /rFqgejLnP2it50yT5krYTCuj+0Rfz27mXGL2CHGiJZjiTDgfeSXC0mLd15slMf0Ac F03mTsNkbnWBBUlsKES7VxqCkyEmz72zI0MA+0BU= From: "wilco at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/94538] [10 Regression] ICE: in extract_constrain_insn_cached, at recog.c:2223 (insn does not satisfy its constraints) with -mcpu=cortex-m23 -mslow-flash-data Date: Tue, 14 Apr 2020 14:42:48 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 10.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: wilco at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: wilco at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Apr 2020 14:42:48 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D94538 --- Comment #10 from Wilco --- (In reply to Christophe Lyon from comment #8) > > Adding Christophe. I'm thinking the best approach right now is to revert > > given -mpure-code doesn't work at all on Thumb-1 targets - it still emi= ts > > literal pools, switch tables etc. That's not pure code! >=20 > Do you have testcases that show these failures? >=20 > I did check some of the problematic testcases in the GCC testsuite when I > committed that patch. Did I miss some of them? >=20 > Can you point me to offending testcases and compiler options so that I can > reproduce them? For example: int x; int f1 (void) { return x; } with eg. -O2 -mcpu=3Dcortex-m0 -mpure-code I get: movs r3, #:upper8_15:#.LC1 lsls r3, #8 adds r3, #:upper0_7:#.LC1 lsls r3, #8 adds r3, #:lower8_15:#.LC1 lsls r3, #8 adds r3, #:lower0_7:#.LC1 @ sp needed ldr r3, [r3] ldr r0, [r3, #40] bx lr That's an extra indirection through a literal... There should only be one l= dr to read x. Big switch tables are produced for any Thumb-1 core, however I would expect Cortex-m0/m23 versions to look almost identical to the Cortex-m3 one, and u= se a sequence of comparisons instead of tables. int f2 (int x, int y) { switch (x) { case 0: return y + 0; case 1: return y + 1; case 2: return y + 2; case 3: return y + 3; case 4: return y + 4; case 5: return y + 5; } return y; } Immediate generation for common cases seems to be screwed up: int f3 (void) { return 0x11000000; } -O2 -mcpu=3Dcortex-m0 -mpure-code: movs r0, #17 lsls r0, r0, #8 lsls r0, r0, #8 lsls r0, r0, #8 bx lr This also regressed Cortex-m23 which previously generated: movs r0, #136 lsls r0, r0, #21 bx lr Similar regressions happen with other immediates: int f3 (void) { return 0x12345678; } -O2 -mcpu=3Dcortex-m23 -mpure-code: movs r0, #86 lsls r0, r0, #8 adds r0, r0, #120 movt r0, 4660 bx lr Previously it was: movw r0, #22136 movt r0, 4660 bx lr Also relocations with a small offset should be handled within the relocatio= n. I'd expect this to never generate an extra addition, let alone an extra lit= eral pool entry: int arr[10]; int *f4 (void) { return &arr[1]; } -O2 -mcpu=3Dcortex-m3 -mpure-code generates the expected: movw r0, #:lower16:.LANCHOR0+4 movt r0, #:upper16:.LANCHOR0+4 bx lr -O2 -mcpu=3Dcortex-m23 -mpure-code generates this: movw r0, #:lower16:.LANCHOR0 movt r0, #:upper16:.LANCHOR0 adds r0, r0, #4 bx lr And cortex-m0 again inserts an extra literal load: movs r3, #:upper8_15:#.LC0 lsls r3, #8 adds r3, #:upper0_7:#.LC0 lsls r3, #8 adds r3, #:lower8_15:#.LC0 lsls r3, #8 adds r3, #:lower0_7:#.LC0 ldr r0, [r3] adds r0, r0, #4 bx lr=