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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/94561] [10 Regression] ICE in ix86_get_ssemov
Date: Tue, 14 Apr 2020 13:02:12 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D94561

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by H.J. Lu <hjl@gcc.gnu.org>:

https://gcc.gnu.org/g:438ffa2a8fac925b1bee8862fa15bc5380c0dffd

commit r10-7715-g438ffa2a8fac925b1bee8862fa15bc5380c0dffd
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Tue Apr 14 06:00:21 2020 -0700

    i386: Remove mode size check in ix86_get_ssemov

    Even though ix86_hard_regno_mode_ok doesn't allow xmm16-xmm31 nor
    ymm16-ymm31 in 128/256 bit modes when AVX512VL is disabled, LRA can
    still generate reg to reg moves with xmm16-xmm31 and ymm16-ymm31 in
    128/256 bit modes.  Remove mode size check in ix86_get_ssemov.

    gcc/

            PR target/94561
            * config/i386/i386.c (ix86_get_ssemov): Remove mode size check.

    gcc/testsuite/

            PR target/94561
            * gcc.target/i386/pr94561.c: New test.=