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From: "jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/94567] [10 Regression] wrong code at -O2 and -O3 on x86_64-linux-gnu
Date: Wed, 15 Apr 2020 17:10:54 +0000	[thread overview]
Message-ID: <bug-94567-4-C2ZV3lxvBG@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-94567-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94567

--- Comment #10 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
So something like:
--- gcc/config/i386/i386.md.jj  2020-03-16 22:56:55.556043275 +0100
+++ gcc/config/i386/i386.md     2020-04-15 19:07:04.405933639 +0200
@@ -8732,8 +8732,20 @@
    && ix86_match_ccmode (insn,
                         /* *testdi_1 requires CCZmode if the mask has bit
                            31 set and all bits above it clear.  */
-                        GET_MODE (operands[2]) == DImode
-                        && INTVAL (operands[3]) + INTVAL (operands[4]) == 32
+                        (GET_MODE (operands[2]) == DImode
+                         && INTVAL (operands[3]) + INTVAL (operands[4]) == 32)
+                        /* If zero_extract mode precision is the same
+                           as len, the SF of the zero_extract
+                           comparison will be the most significant
+                           extracted bit, but this could be matched
+                           after splitting only for pos 0 len all bits
+                           trivial extractions.  Require CCZmode.  */
+                        || (GET_MODE_PRECISION (<MODE>mode)
+                            == INTVAL (operands[3]))
+                        /* Otherwise, require CCZmode if we'd use a mask
+                           with the most significant bit set.  */
+                        || (INTVAL (operands[3]) + INTVAL (operands[4])
+                            == GET_MODE (operands[2]))
                         ? CCZmode : CCNOmode)"
   "#"
   "&& 1"
@@ -8758,7 +8770,12 @@
     }

   /* Small HImode tests can be converted to QImode.  */
-  if (register_operand (val, HImode) && pos + len <= 8)
+  if (register_operand (val, HImode)
+      && (pos + len < 8
+         /* If the mask would include all bits, ensure we don't
+            care about the SF.  */
+         || (pos + len == 8
+             && GET_MODE (operands[0]) == CCZmode)))
     {
       val = gen_lowpart (QImode, val);
       mode = QImode;

  parent reply	other threads:[~2020-04-15 17:10 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-12  2:49 [Bug tree-optimization/94567] New: " qrzhang at gatech dot edu
2020-04-14  6:41 ` [Bug rtl-optimization/94567] [10 Regression] " marxin at gcc dot gnu.org
2020-04-14 11:28 ` law at redhat dot com
2020-04-14 11:45 ` [Bug target/94567] " rguenth at gcc dot gnu.org
2020-04-14 11:48 ` rguenth at gcc dot gnu.org
2020-04-14 11:59 ` law at redhat dot com
2020-04-14 12:45 ` rguenth at gcc dot gnu.org
2020-04-14 13:20 ` law at redhat dot com
2020-04-15  9:57 ` rguenth at gcc dot gnu.org
2020-04-15 16:57 ` jakub at gcc dot gnu.org
2020-04-15 17:10 ` jakub at gcc dot gnu.org [this message]
2020-04-15 17:14 ` law at redhat dot com
2020-04-15 17:48 ` jakub at gcc dot gnu.org
2020-04-15 23:12 ` law at redhat dot com
2020-04-16 12:30 ` jakub at gcc dot gnu.org
2020-04-16 22:45 ` law at redhat dot com
2020-04-17 14:58 ` cvs-commit at gcc dot gnu.org
2020-04-17 15:11 ` jakub at gcc dot gnu.org

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