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* [Bug target/94584] New: memw is missing before u8/u16 volatile loads
@ 2020-04-13 20:24 jcmvbkbc at gcc dot gnu.org
2020-04-14 23:56 ` [Bug target/94584] " cvs-commit at gcc dot gnu.org
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: jcmvbkbc at gcc dot gnu.org @ 2020-04-13 20:24 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94584
Bug ID: 94584
Summary: memw is missing before u8/u16 volatile loads
Product: gcc
Version: 10.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: jcmvbkbc at gcc dot gnu.org
Target Milestone: ---
Created attachment 48262
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=48262&action=edit
minimal reproducer
xtensa-elf-gcc -O2 -S volatile.c results in the following code:
.file "volatile.c"
.text
.align 4
.global load32
.type load32, @function
load32:
entry sp, 32
memw
l32i.n a2, a2, 0
retw.n
.size load32, .-load32
.align 4
.global load16s
.type load16s, @function
load16s:
entry sp, 32
l16ui a2, a2, 0
sext a2, a2, 15
retw.n
.size load16s, .-load16s
.align 4
.global load16u
.type load16u, @function
load16u:
entry sp, 32
l16ui a2, a2, 0
retw.n
.size load16u, .-load16u
.align 4
.global load8
.type load8, @function
load8:
entry sp, 32
l8ui a2, a2, 0
retw.n
.size load8, .-load8
.ident "GCC: (GNU) 9.2.0"
There must be memw before l16ui and l8ui.
^ permalink raw reply [flat|nested] 5+ messages in thread* [Bug target/94584] memw is missing before u8/u16 volatile loads
2020-04-13 20:24 [Bug target/94584] New: memw is missing before u8/u16 volatile loads jcmvbkbc at gcc dot gnu.org
@ 2020-04-14 23:56 ` cvs-commit at gcc dot gnu.org
2020-04-15 2:21 ` jcmvbkbc at gcc dot gnu.org
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2020-04-14 23:56 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94584
--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Max Filippov <jcmvbkbc@gcc.gnu.org>:
https://gcc.gnu.org/g:a288e202c5e50704968685fc2922d159335be2cb
commit r10-7728-ga288e202c5e50704968685fc2922d159335be2cb
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: Mon Apr 13 13:26:04 2020 -0700
xtensa: fix PR target/94584
Patterns zero_extendhisi2, zero_extendqisi2 and extendhisi2_internal can
load value from memory, but they don't treat volatile memory correctly.
Add %v1 before load instructions to emit 'memw' instruction when
-mserialize-volatile is in effect.
2020-04-14 Max Filippov <jcmvbkbc@gmail.com>
gcc/
* config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
(extendhisi2_internal): Add %v1 before the load instructions.
gcc/testsuite/
* gcc.target/xtensa/pr94584.c: New test.
^ permalink raw reply [flat|nested] 5+ messages in thread* [Bug target/94584] memw is missing before u8/u16 volatile loads
2020-04-13 20:24 [Bug target/94584] New: memw is missing before u8/u16 volatile loads jcmvbkbc at gcc dot gnu.org
2020-04-14 23:56 ` [Bug target/94584] " cvs-commit at gcc dot gnu.org
@ 2020-04-15 2:21 ` jcmvbkbc at gcc dot gnu.org
2020-04-15 21:11 ` cvs-commit at gcc dot gnu.org
2020-04-15 21:24 ` cvs-commit at gcc dot gnu.org
3 siblings, 0 replies; 5+ messages in thread
From: jcmvbkbc at gcc dot gnu.org @ 2020-04-15 2:21 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94584
jcmvbkbc at gcc dot gnu.org changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Status|UNCONFIRMED |RESOLVED
--- Comment #2 from jcmvbkbc at gcc dot gnu.org ---
Fixed in the master.
^ permalink raw reply [flat|nested] 5+ messages in thread* [Bug target/94584] memw is missing before u8/u16 volatile loads
2020-04-13 20:24 [Bug target/94584] New: memw is missing before u8/u16 volatile loads jcmvbkbc at gcc dot gnu.org
2020-04-14 23:56 ` [Bug target/94584] " cvs-commit at gcc dot gnu.org
2020-04-15 2:21 ` jcmvbkbc at gcc dot gnu.org
@ 2020-04-15 21:11 ` cvs-commit at gcc dot gnu.org
2020-04-15 21:24 ` cvs-commit at gcc dot gnu.org
3 siblings, 0 replies; 5+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2020-04-15 21:11 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94584
--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Max Filippov
<jcmvbkbc@gcc.gnu.org>:
https://gcc.gnu.org/g:f45b87f786809997d2f8d418ab10de6640149422
commit r8-10182-gf45b87f786809997d2f8d418ab10de6640149422
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: Mon Apr 13 13:26:04 2020 -0700
xtensa: backport fix for PR target/94584
Patterns zero_extendhisi2, zero_extendqisi2 and extendhisi2_internal can
load value from memory, but they don't treat volatile memory correctly.
Add %v1 before load instructions to emit 'memw' instruction when
-mserialize-volatile is in effect.
2020-04-15 Max Filippov <jcmvbkbc@gmail.com>
gcc/
* config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
(extendhisi2_internal): Add %v1 before the load instructions.
gcc/testsuite/
* gcc.target/xtensa/pr94584.c: New test.
^ permalink raw reply [flat|nested] 5+ messages in thread* [Bug target/94584] memw is missing before u8/u16 volatile loads
2020-04-13 20:24 [Bug target/94584] New: memw is missing before u8/u16 volatile loads jcmvbkbc at gcc dot gnu.org
` (2 preceding siblings ...)
2020-04-15 21:11 ` cvs-commit at gcc dot gnu.org
@ 2020-04-15 21:24 ` cvs-commit at gcc dot gnu.org
3 siblings, 0 replies; 5+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2020-04-15 21:24 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94584
--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Max Filippov
<jcmvbkbc@gcc.gnu.org>:
https://gcc.gnu.org/g:79b59676531631331b9353107f7d40c887852433
commit r9-8501-g79b59676531631331b9353107f7d40c887852433
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: Mon Apr 13 13:26:04 2020 -0700
xtensa: backport fix for PR target/94584
Patterns zero_extendhisi2, zero_extendqisi2 and extendhisi2_internal can
load value from memory, but they don't treat volatile memory correctly.
Add %v1 before load instructions to emit 'memw' instruction when
-mserialize-volatile is in effect.
2020-04-15 Max Filippov <jcmvbkbc@gmail.com>
gcc/
* config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
(extendhisi2_internal): Add %v1 before the load instructions.
gcc/testsuite/
* gcc.target/xtensa/pr94584.c: New test.
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-04-15 21:24 UTC | newest]
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2020-04-13 20:24 [Bug target/94584] New: memw is missing before u8/u16 volatile loads jcmvbkbc at gcc dot gnu.org
2020-04-14 23:56 ` [Bug target/94584] " cvs-commit at gcc dot gnu.org
2020-04-15 2:21 ` jcmvbkbc at gcc dot gnu.org
2020-04-15 21:11 ` cvs-commit at gcc dot gnu.org
2020-04-15 21:24 ` cvs-commit at gcc dot gnu.org
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