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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/94584] memw is missing before u8/u16 volatile loads Date: Wed, 15 Apr 2020 21:24:05 +0000 [thread overview] Message-ID: <bug-94584-4-4kul8y9TRz@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-94584-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94584 --- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The releases/gcc-9 branch has been updated by Max Filippov <jcmvbkbc@gcc.gnu.org>: https://gcc.gnu.org/g:79b59676531631331b9353107f7d40c887852433 commit r9-8501-g79b59676531631331b9353107f7d40c887852433 Author: Max Filippov <jcmvbkbc@gmail.com> Date: Mon Apr 13 13:26:04 2020 -0700 xtensa: backport fix for PR target/94584 Patterns zero_extendhisi2, zero_extendqisi2 and extendhisi2_internal can load value from memory, but they don't treat volatile memory correctly. Add %v1 before load instructions to emit 'memw' instruction when -mserialize-volatile is in effect. 2020-04-15 Max Filippov <jcmvbkbc@gmail.com> gcc/ * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2) (extendhisi2_internal): Add %v1 before the load instructions. gcc/testsuite/ * gcc.target/xtensa/pr94584.c: New test.
prev parent reply other threads:[~2020-04-15 21:24 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-13 20:24 [Bug target/94584] New: " jcmvbkbc at gcc dot gnu.org 2020-04-14 23:56 ` [Bug target/94584] " cvs-commit at gcc dot gnu.org 2020-04-15 2:21 ` jcmvbkbc at gcc dot gnu.org 2020-04-15 21:11 ` cvs-commit at gcc dot gnu.org 2020-04-15 21:24 ` cvs-commit at gcc dot gnu.org [this message]
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