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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/94584] memw is missing before u8/u16 volatile loads
Date: Tue, 14 Apr 2020 23:56:08 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D94584

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Max Filippov <jcmvbkbc@gcc.gnu.org>:

https://gcc.gnu.org/g:a288e202c5e50704968685fc2922d159335be2cb

commit r10-7728-ga288e202c5e50704968685fc2922d159335be2cb
Author: Max Filippov <jcmvbkbc@gmail.com>
Date:   Mon Apr 13 13:26:04 2020 -0700

    xtensa: fix PR target/94584

    Patterns zero_extendhisi2, zero_extendqisi2 and extendhisi2_internal can
    load value from memory, but they don't treat volatile memory correctly.
    Add %v1 before load instructions to emit 'memw' instruction when
    -mserialize-volatile is in effect.

    2020-04-14  Max Filippov  <jcmvbkbc@gmail.com>
    gcc/
            * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
            (extendhisi2_internal): Add %v1 before the load instructions.

    gcc/testsuite/
            * gcc.target/xtensa/pr94584.c: New test.=