public inbox for gcc-bugs@sourceware.org
help / color / mirror / Atom feed
* [Bug target/94606] New: [10 Regression] ICE creating fixed-length SVE predicate
@ 2020-04-15 12:38 rsandifo at gcc dot gnu.org
2020-04-15 12:39 ` [Bug target/94606] " rsandifo at gcc dot gnu.org
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: rsandifo at gcc dot gnu.org @ 2020-04-15 12:38 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94606
Bug ID: 94606
Summary: [10 Regression] ICE creating fixed-length SVE
predicate
Product: gcc
Version: 10.0
Status: UNCONFIRMED
Keywords: ice-on-valid-code
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: rsandifo at gcc dot gnu.org
Target Milestone: ---
Target: aarch64*-*-*
Compiling the following testcase with -O3 -march=armv8.2-a+sve
-msve-vector-bits=256:
const short mask[] = { 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 1, 1, 1 };
int
foo (short *restrict x, short *restrict y)
{
for (int i = 0; i < 16; ++i)
if (mask[i])
x[i] += y[i];
}
gives:
error: unrecognizable insn:
10 | }
| ^
(insn 10 9 11 2 (set (reg:VNx16BI 105)
(and:VNx16BI (xor:VNx16BI (reg:VNx8BI 103)
(reg:VNx16BI 104))
(reg:VNx16BI 104))) "/tmp/bar.c":9:12 -1
(nil))
during RTL pass: vregs
because the first operand to the xor has the wrong mode.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/94606] [10 Regression] ICE creating fixed-length SVE predicate
2020-04-15 12:38 [Bug target/94606] New: [10 Regression] ICE creating fixed-length SVE predicate rsandifo at gcc dot gnu.org
@ 2020-04-15 12:39 ` rsandifo at gcc dot gnu.org
2020-04-15 12:58 ` rguenth at gcc dot gnu.org
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: rsandifo at gcc dot gnu.org @ 2020-04-15 12:39 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94606
rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |ASSIGNED
Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org
Ever confirmed|0 |1
Last reconfirmed| |2020-04-15
--- Comment #1 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> ---
Mine.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/94606] [10 Regression] ICE creating fixed-length SVE predicate
2020-04-15 12:38 [Bug target/94606] New: [10 Regression] ICE creating fixed-length SVE predicate rsandifo at gcc dot gnu.org
2020-04-15 12:39 ` [Bug target/94606] " rsandifo at gcc dot gnu.org
@ 2020-04-15 12:58 ` rguenth at gcc dot gnu.org
2020-04-16 14:45 ` cvs-commit at gcc dot gnu.org
2020-04-16 14:48 ` rsandifo at gcc dot gnu.org
3 siblings, 0 replies; 5+ messages in thread
From: rguenth at gcc dot gnu.org @ 2020-04-15 12:58 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94606
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Target Milestone|--- |10.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/94606] [10 Regression] ICE creating fixed-length SVE predicate
2020-04-15 12:38 [Bug target/94606] New: [10 Regression] ICE creating fixed-length SVE predicate rsandifo at gcc dot gnu.org
2020-04-15 12:39 ` [Bug target/94606] " rsandifo at gcc dot gnu.org
2020-04-15 12:58 ` rguenth at gcc dot gnu.org
@ 2020-04-16 14:45 ` cvs-commit at gcc dot gnu.org
2020-04-16 14:48 ` rsandifo at gcc dot gnu.org
3 siblings, 0 replies; 5+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2020-04-16 14:45 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94606
--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Richard Sandiford <rsandifo@gcc.gnu.org>:
https://gcc.gnu.org/g:26bebf576ddcdcfb596f07e8c2896f17c48516e7
commit r10-7759-g26bebf576ddcdcfb596f07e8c2896f17c48516e7
Author: Richard Sandiford <richard.sandiford@arm.com>
Date: Wed Apr 15 13:52:20 2020 +0100
aarch64: Fix mismatched SVE predicate modes [PR94606]
For this testcase we ended up generating the invalid rtl:
(insn 10 9 11 2 (set (reg:VNx16BI 105)
(and:VNx16BI (xor:VNx16BI (reg:VNx8BI 103)
(reg:VNx16BI 104))
(reg:VNx16BI 104))) "/tmp/bar.c":9:12 -1
(nil))
Fixed by taking the VNx16BI lowpart. It's safe to do that here because
the gp (r104) masks out the extra odd-indexed bits.
2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/
PR target/94606
* config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor):
Take
the VNx16BI lowpart of the recursively-generated constant.
gcc/testsuite/
PR target/94606
* gcc.dg/vect/pr94606.c: New test.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/94606] [10 Regression] ICE creating fixed-length SVE predicate
2020-04-15 12:38 [Bug target/94606] New: [10 Regression] ICE creating fixed-length SVE predicate rsandifo at gcc dot gnu.org
` (2 preceding siblings ...)
2020-04-16 14:45 ` cvs-commit at gcc dot gnu.org
@ 2020-04-16 14:48 ` rsandifo at gcc dot gnu.org
3 siblings, 0 replies; 5+ messages in thread
From: rsandifo at gcc dot gnu.org @ 2020-04-16 14:48 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94606
rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|ASSIGNED |RESOLVED
Resolution|--- |FIXED
--- Comment #3 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> ---
Fixed on master.
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-04-16 14:48 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-15 12:38 [Bug target/94606] New: [10 Regression] ICE creating fixed-length SVE predicate rsandifo at gcc dot gnu.org
2020-04-15 12:39 ` [Bug target/94606] " rsandifo at gcc dot gnu.org
2020-04-15 12:58 ` rguenth at gcc dot gnu.org
2020-04-16 14:45 ` cvs-commit at gcc dot gnu.org
2020-04-16 14:48 ` rsandifo at gcc dot gnu.org
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).