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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/94606] [10 Regression] ICE creating fixed-length SVE
 predicate
Date: Thu, 16 Apr 2020 14:45:52 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D94606

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Richard Sandiford <rsandifo@gcc.gnu.o=
rg>:

https://gcc.gnu.org/g:26bebf576ddcdcfb596f07e8c2896f17c48516e7

commit r10-7759-g26bebf576ddcdcfb596f07e8c2896f17c48516e7
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Wed Apr 15 13:52:20 2020 +0100

    aarch64: Fix mismatched SVE predicate modes [PR94606]

    For this testcase we ended up generating the invalid rtl:

    (insn 10 9 11 2 (set (reg:VNx16BI 105)
            (and:VNx16BI (xor:VNx16BI (reg:VNx8BI 103)
                    (reg:VNx16BI 104))
                (reg:VNx16BI 104))) "/tmp/bar.c":9:12 -1
         (nil))

    Fixed by taking the VNx16BI lowpart.  It's safe to do that here because
    the gp (r104) masks out the extra odd-indexed bits.

    2020-04-16  Richard Sandiford  <richard.sandiford@arm.com>

    gcc/
            PR target/94606
            * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor):
Take
            the VNx16BI lowpart of the recursively-generated constant.

    gcc/testsuite/
            PR target/94606
            * gcc.dg/vect/pr94606.c: New test.=