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From: "rsandifo at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/94606] New: [10 Regression] ICE creating fixed-length
 SVE predicate
Date: Wed, 15 Apr 2020 12:38:39 +0000
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X-Bugzilla-Version: 10.0
X-Bugzilla-Keywords: ice-on-valid-code
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D94606

            Bug ID: 94606
           Summary: [10 Regression] ICE creating fixed-length SVE
                    predicate
           Product: gcc
           Version: 10.0
            Status: UNCONFIRMED
          Keywords: ice-on-valid-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: rsandifo at gcc dot gnu.org
  Target Milestone: ---
            Target: aarch64*-*-*

Compiling the following testcase with -O3 -march=3Darmv8.2-a+sve
-msve-vector-bits=3D256:

const short mask[] =3D { 0, 0, 0, 0, 0, 0, 0, 0,
                       0, 0, 0, 1, 1, 1, 1, 1 };

int
foo (short *restrict x, short *restrict y)
{
  for (int i =3D 0; i < 16; ++i)
    if (mask[i])
      x[i] +=3D y[i];
}

gives:

error: unrecognizable insn:
   10 | }
      | ^
(insn 10 9 11 2 (set (reg:VNx16BI 105)
        (and:VNx16BI (xor:VNx16BI (reg:VNx8BI 103)
                (reg:VNx16BI 104))
            (reg:VNx16BI 104))) "/tmp/bar.c":9:12 -1
     (nil))
during RTL pass: vregs

because the first operand to the xor has the wrong mode.=