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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/94613] S/390, powerpc: Wrong code generated for vec_sel builtin Date: Thu, 28 Oct 2021 03:18:14 +0000 [thread overview] Message-ID: <bug-94613-4-B7D1GEncW3@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-94613-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94613 --- Comment #15 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Xiong Hu Luo <luoxhu@gcc.gnu.org>: https://gcc.gnu.org/g:9222481ffc69a6c0b73ec81e1bf04289fa3db0ed commit r12-4757-g9222481ffc69a6c0b73ec81e1bf04289fa3db0ed Author: Xionghu Luo <luoxhu@linux.ibm.com> Date: Wed Oct 27 21:21:20 2021 -0500 rs6000: Fix wrong code generation for vec_sel [PR94613] The vsel instruction is a bit-wise select instruction. Using an IF_THEN_ELSE to express it in RTL is wrong and leads to wrong code being generated in the combine pass. Per element selection is a subset of per bit-wise selection,with the patch the pattern is written using bit operations. But there are 8 different patterns to define "op0 := (op1 & ~op3) | (op2 & op3)": (~op3&op1) | (op3&op2), (~op3&op1) | (op2&op3), (op3&op2) | (~op3&op1), (op2&op3) | (~op3&op1), (op1&~op3) | (op3&op2), (op1&~op3) | (op2&op3), (op3&op2) | (op1&~op3), (op2&op3) | (op1&~op3), The latter 4 cases does not follow canonicalisation rules, non-canonical RTL is invalid RTL in vregs pass. Secondly, combine pass will swap (op1&~op3) to (~op3&op1) by commutative canonical, which could reduce it to the FIRST 4 patterns, but it won't swap (op2&op3) | (~op3&op1) to (~op3&op1) | (op2&op3), so this patch handles it with 4 patterns with different NOT op3 position and check equality inside it. Tested pass on P7, P8 and P9. gcc/ChangeLog: 2021-10-28 Xionghu Luo <luoxhu@linux.ibm.com> PR target/94613 * config/rs6000/altivec.md (*altivec_vsel<mode>): Change to ... (altivec_vsel<mode>): ... this and update define. (*altivec_vsel<mode>_uns): Delete. (altivec_vsel<mode>2): New define_insn. (altivec_vsel<mode>3): Likewise. (altivec_vsel<mode>4): Likewise. * config/rs6000/rs6000-call.c (altivec_expand_vec_sel_builtin): New. (altivec_expand_builtin): Call altivec_expand_vec_sel_builtin to expand vel_sel. * config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Use bit-wise selection instead of per element. * config/rs6000/vector.md: * config/rs6000/vsx.md (*vsx_xxsel<mode>): Change to ... (vsx_xxsel<mode>): ... this and update define. (*vsx_xxsel<mode>_uns): Delete. (vsx_xxsel<mode>2): New define_insn. (vsx_xxsel<mode>3): Likewise. (vsx_xxsel<mode>4): Likewise. gcc/testsuite/ChangeLog: 2021-10-28 Xionghu Luo <luoxhu@linux.ibm.com> PR target/94613 * gcc.target/powerpc/pr94613.c: New test.
next prev parent reply other threads:[~2021-10-28 3:18 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-16 7:01 [Bug rtl-optimization/94613] New: combine: Wrong code due to splitting a simplified IF_THEN_ELSE krebbel at gcc dot gnu.org 2020-04-16 7:02 ` [Bug rtl-optimization/94613] " krebbel at gcc dot gnu.org 2020-04-16 7:05 ` krebbel at gcc dot gnu.org 2020-04-16 7:05 ` krebbel at gcc dot gnu.org 2020-04-16 7:09 ` krebbel at gcc dot gnu.org 2020-04-16 7:10 ` rguenth at gcc dot gnu.org 2020-04-16 7:15 ` rguenth at gcc dot gnu.org 2020-04-16 7:37 ` krebbel at gcc dot gnu.org 2020-04-16 8:21 ` [Bug target/94613] Wrong code generated for vec_sel builtin krebbel at gcc dot gnu.org 2020-04-16 8:28 ` [Bug target/94613] S/390: " krebbel at gcc dot gnu.org 2020-04-16 21:18 ` segher at gcc dot gnu.org 2020-04-20 17:39 ` [Bug target/94613] S/390, powerpc: " cvs-commit at gcc dot gnu.org 2020-05-04 8:39 ` cvs-commit at gcc dot gnu.org 2020-05-04 8:43 ` cvs-commit at gcc dot gnu.org 2020-05-07 11:56 ` jakub at gcc dot gnu.org 2020-07-23 6:52 ` rguenth at gcc dot gnu.org 2021-04-08 12:02 ` rguenth at gcc dot gnu.org 2021-05-04 12:32 ` rguenth at gcc dot gnu.org 2021-05-27 0:57 ` luoxhu at gcc dot gnu.org 2021-10-28 3:18 ` cvs-commit at gcc dot gnu.org [this message] 2021-10-28 3:18 ` cvs-commit at gcc dot gnu.org 2021-10-28 6:04 ` luoxhu at gcc dot gnu.org
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