[Bug target/94678] New: aarch64: unexpected result with -mgeneral-regs-only and sve

["felix.yang at huawei dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94678

            Bug ID: 94678
           Summary: aarch64: unexpected result with -mgeneral-regs-only
                    and sve
           Product: gcc
           Version: 10.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: felix.yang at huawei dot com
                CC: richard.sandiford at arm dot com
  Target Milestone: ---
            Target: aarch64

It looks like there are several issues out there for aarch64 sve codegen with
-mgeneral-regs-only.

>> test1.c:
#pragma GCC aarch64 "arm_sve.h" 

svbool_t
f1()
{
  return svptrue_b8 ();
}

$aarch64-linux-gnu-gcc -S -march=armv8.2-a+sve -mgeneral-regs-only test1.c 

Assembly output:
f1:
.LFB0:
        .cfi_startproc
        ptrue   p0.b, all   <==== predicate register is used here even with
-mgeneral-regs-only 
        ret
        .cfi_endproc
.LFE0:

>> test2.c:
#pragma GCC aarch64 "arm_sve.h"

svint8_t
f2 (svbool_t *x, svint8_t *y)
{
  return svadd_m (*x, *y, 1);
}

$aarch64-linux-gnu-gcc -S -march=armv8.2-a+sve -mgeneral-regs-only test2.c 

This will trigger an ICE.

We do ISA extension checks for SVE in
check_required_extensions(aarch64-sve-builtins.cc), I think we may also need to
check -mgeneral-regs-only there and issue an error message when this option is
specified.  This would be cheap as compared with adding &&
TARGET_GENERAL_REGS_ONLY to TARGET_SVE and similar macros.  I have created a
patch for that.