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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/94735] MVE vector load/store pair getting removed with -O2.
Date: Thu, 04 Jun 2020 14:55:53 +0000 [thread overview]
Message-ID: <bug-94735-4-UV5xQhxBIv@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-94735-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94735
--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by SRINATH PARVATHANENI
<sripar01@gcc.gnu.org>:
https://gcc.gnu.org/g:9a810e57c4e6af54d29c325a013f451ade2b85e8
commit r11-934-g9a810e57c4e6af54d29c325a013f451ade2b85e8
Author: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Date: Thu Jun 4 15:41:29 2020 +0100
[ARM]: Correct the grouping of operands in MVE vector scatter store
intrinsics (PR94735).
The operands in RTL patterns of MVE vector scatter store intrinsics are
wrongly grouped,
because of which few vector loads and stores instructions are wrongly
getting optimized
out with -O2.
A new predicate "mve_scatter_memory" is defined in this patch, this
predicate returns TRUE on
matching: (mem(reg)) for MVE scatter store intrinsics.
This patch fixes the issue by adding define_expand pattern with
"mve_scatter_memory" predicate
and calls the corresponding define_insn by passing register_operand as
first argument.
This register_operand is extracted from the operand with
"mve_scatter_memory" predicate in
define_expand pattern.
gcc/ChangeLog:
2020-06-01 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
PR target/94735
* config/arm/predicates.md (mve_scatter_memory): Define to
match (mem (reg)) for scatter store memory.
* config/arm/mve.md (mve_vstrbq_scatter_offset_<supf><mode>):
Modify
define_insn to define_expand.
(mve_vstrbq_scatter_offset_p_<supf><mode>): Likewise.
(mve_vstrhq_scatter_offset_<supf><mode>): Likewise.
(mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise.
(mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise.
(mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise.
(mve_vstrdq_scatter_offset_<supf>v2di): Likewise.
(mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise.
(mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise.
(mve_vstrhq_scatter_offset_fv8hf): Likewise.
(mve_vstrhq_scatter_offset_p_fv8hf): Likewise.
(mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise.
(mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise.
(mve_vstrwq_scatter_offset_fv4sf): Likewise.
(mve_vstrwq_scatter_offset_p_fv4sf): Likewise.
(mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise.
(mve_vstrwq_scatter_offset_<supf>v4si): Likewise.
(mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise.
(mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise.
(mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise.
(mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise.
(mve_vstrbq_scatter_offset_<supf><mode>_insn): Define insn for
scatter
stores.
(mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
(mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
(mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
(mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
(mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
(mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
(mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
(mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
(mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
(mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
(mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
(mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
(mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
(mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
(mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
(mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
(mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
(mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
(mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
(mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
gcc/testsuite/ChangeLog:
2020-06-01 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
PR target/94735
* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_base.c: New
test.
* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_base_p.c:
Likewise.
* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_offset.c:
Likewise.
* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_offset_p.c:
Likewise.
*
gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c:
Likewise.
*
gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c:
Likewise.
next prev parent reply other threads:[~2020-06-04 14:55 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-23 17:22 [Bug c/94735] New: " sripar01 at gcc dot gnu.org
2020-04-23 17:24 ` [Bug c/94735] " sripar01 at gcc dot gnu.org
2020-06-04 14:55 ` cvs-commit at gcc dot gnu.org [this message]
2020-06-16 13:54 ` [Bug target/94735] " cvs-commit at gcc dot gnu.org
2020-06-18 11:08 ` sripar01 at gcc dot gnu.org
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