[Bug target/94908] Failure to optimally optimize certain shuffle patterns

["ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94908

--- Comment #9 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Hongtao.liu from comment #8)

> I'm thinking of something like below so it can be matched both by
> expand_vselect_vconcat in ix86_expand_vec_perm_const_1 and patterns created
> by pass_combine(theoretically).
> 
> +(define_insn_and_split "*sse4_1_insertps_1"
> +  [(set (match_operand:VI4F_128 0 "register_operand")
> +       (vec_select:VI4F_128
> +         (vec_concat:<ssedoublevecmode>
> +           (match_operand:VI4F_128 1 "register_operand")
> +           (match_operand:VI4F_128 2 "register_operand"))
> +         (match_parallel 3 "insertps_parallel"
> +           [(match_operand 4 "const_int_operand")])))]
> +  "TARGET_SSE4_1 && ix86_pre_reload_split ()"
> +  "#"
> +  "&& 1"

If you want to go that way, then the resulting pattern should look like
combination of:

(define_insn "*vec_setv4sf_sse4_1"
  [(set (match_operand:V4SF 0 "register_operand" "=Yr,*x,v")
        (vec_merge:V4SF
          (vec_duplicate:V4SF
            (match_operand:SF 2 "nonimmediate_operand" "Yrm,*xm,vm"))
          (match_operand:V4SF 1 "register_operand" "0,0,v")
          (match_operand:SI 3 "const_0_to_3_operand")))]
  "TARGET_SSE4_1
   && ((unsigned) exact_log2 (INTVAL (operands[3]))
       < GET_MODE_NUNITS (V4SFmode))"

(define_insn_and_split "*sse4_1_extractps"
  [(set (match_operand:SF 0 "nonimmediate_operand" "=rm,rm,rm,Yv,Yv")
        (vec_select:SF
          (match_operand:V4SF 1 "register_operand" "Yr,*x,v,0,v")
          (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
  "TARGET_SSE4_1"

where the later pattern propagates into the former in place of operand 2. This
combination is created only for scalar insert of an extracted value, so I doubt
it is ever created...