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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/94962] Suboptimal AVX2 code for
 _mm256_zextsi128_si256(_mm_set1_epi8(-1))
Date: Fri, 23 Sep 2022 05:29:28 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D94962

--- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:

https://gcc.gnu.org/g:a282f086ef26d90e9785e992cd09a0d118b24695

commit r13-2804-ga282f086ef26d90e9785e992cd09a0d118b24695
Author: Hu, Lin1 <lin1.hu@intel.com>
Date:   Tue Sep 13 16:28:54 2022 +0800

    i386: Optimize code generation of
__mm256_zextsi128_si256(__mm_set1_epi8(-1))

    gcc/ChangeLog:

            PR target/94962
            * config/i386/constraints.md (BH): New define_constraint.
            * config/i386/i386.cc (standard_sse_constant_p): Add return
            3/4 when operand matches new predicate.
            (standard_sse_constant_opcode): Add new alternative branch to
            return "vpcmpeqd".
            * config/i386/predicates.md
            (vector_all_ones_zero_extend_half_operand): New define_predicat=
e.
            (vector_all_ones_zero_extend_quarter_operand): Ditto.
            * config/i386/sse.md: Add constraint to insn "mov<mode>_interna=
l".

    gcc/testsuite/ChangeLog:

            PR target/94962
            * gcc.target/i386/avx256-unaligned-load-1.c: Modify test.
            * gcc.target/i386/avx256-unaligned-store-1.c: Ditto.
            * gcc.target/i386/avx256-unaligned-store-2.c: Ditto.
            * gcc.target/i386/avx256-unaligned-store-3.c: Ditto.
            * gcc.target/i386/pr94962-1.c: New test.
            * gcc.target/i386/pr94962-2.c: Ditto.
            * gcc.target/i386/pr94962-3.c: Ditto.
            * gcc.target/i386/pr94962-4.c: Ditto.=