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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/95046] Vectorize V2SFmode operations
Date: Mon, 11 May 2020 09:17:16 +0000 [thread overview]
Message-ID: <bug-95046-4-6fxP7caM8b@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-95046-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046
--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:
https://gcc.gnu.org/g:7c355156aa20eaec7401d7c66f6a6cfbe597abc2
commit r11-263-g7c355156aa20eaec7401d7c66f6a6cfbe597abc2
Author: Uros Bizjak <ubizjak@gmail.com>
Date: Mon May 11 11:16:31 2020 +0200
i386: Vectorize basic V2SFmode operations [PR94913]
Enable V2SFmode vectorization and vectorize V2SFmode PLUS,
MINUS, MULT, MIN and MAX operations using XMM registers.
To avoid unwanted secondary effects (e.g. exceptions), load values
to XMM registers using MOVQ that clears high bits of the XMM
register outside V2SFmode.
The compiler now vectorizes e.g.:
float r[2], a[2], b[2];
void
test_plus (void)
{
for (int i = 0; i < 2; i++)
r[i] = a[i] + b[i];
}
to:
movq a(%rip), %xmm0
movq b(%rip), %xmm1
addps %xmm1, %xmm0
movlps %xmm0, r(%rip)
ret
gcc/ChangeLog:
PR target/95046
* config/i386/i386.c (ix86_vector_mode_supported_p):
Vectorize 3dNOW! vector modes for TARGET_MMX_WITH_SSE.
* config/i386/mmx.md (*mov<mode>_internal): Do not set
mode of alternative 13 to V2SF for TARGET_MMX_WITH_SSE.
(mmx_addv2sf3): Change operand predicates from
nonimmediate_operand to register_mmxmem_operand.
(addv2sf3): New expander.
(*mmx_addv2sf3): Add SSE/AVX alternatives. Change operand
predicates from nonimmediate_operand to register_mmxmem_operand.
Enable instruction pattern for TARGET_MMX_WITH_SSE.
(mmx_subv2sf3): Change operand predicate from
nonimmediate_operand to register_mmxmem_operand.
(mmx_subrv2sf3): Ditto.
(subv2sf3): New expander.
(*mmx_subv2sf3): Add SSE/AVX alternatives. Change operand
predicates from nonimmediate_operand to register_mmxmem_operand.
Enable instruction pattern for TARGET_MMX_WITH_SSE.
(mmx_mulv2sf3): Change operand predicates from
nonimmediate_operand to register_mmxmem_operand.
(mulv2sf3): New expander.
(*mmx_mulv2sf3): Add SSE/AVX alternatives. Change operand
predicates from nonimmediate_operand to register_mmxmem_operand.
Enable instruction pattern for TARGET_MMX_WITH_SSE.
(mmx_<code>v2sf3): Change operand predicates from
nonimmediate_operand to register_mmxmem_operand.
(<code>v2sf3): New expander.
(*mmx_<code>v2sf3): Add SSE/AVX alternatives. Change operand
predicates from nonimmediate_operand to register_mmxmem_operand.
Enable instruction pattern for TARGET_MMX_WITH_SSE.
(mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
testsuite/ChangeLog:
PR target/95046
* gcc.target/i386/pr95046-1.c: New test.
next prev parent reply other threads:[~2020-05-11 9:17 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-11 7:12 [Bug target/95046] New: " ubizjak at gmail dot com
2020-05-11 7:13 ` [Bug target/95046] " ubizjak at gmail dot com
2020-05-11 7:13 ` ubizjak at gmail dot com
2020-05-11 9:17 ` cvs-commit at gcc dot gnu.org [this message]
2020-05-11 14:39 ` cvs-commit at gcc dot gnu.org
2020-05-11 18:13 ` cvs-commit at gcc dot gnu.org
2020-05-12 15:06 ` cvs-commit at gcc dot gnu.org
2020-05-12 15:08 ` cvs-commit at gcc dot gnu.org
2020-05-12 16:38 ` cvs-commit at gcc dot gnu.org
2020-05-12 17:25 ` cvs-commit at gcc dot gnu.org
2020-05-14 7:16 ` cvs-commit at gcc dot gnu.org
2020-05-14 11:48 ` cvs-commit at gcc dot gnu.org
2020-05-14 17:52 ` cvs-commit at gcc dot gnu.org
2020-05-15 7:25 ` cvs-commit at gcc dot gnu.org
2020-05-15 8:03 ` cvs-commit at gcc dot gnu.org
2020-12-10 9:45 ` ubizjak at gmail dot com
2021-06-29 17:18 ` cvs-commit at gcc dot gnu.org
2021-12-24 16:10 ` cvs-commit at gcc dot gnu.org
2021-12-27 9:12 ` cvs-commit at gcc dot gnu.org
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