From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 991BC386F82C; Fri, 15 May 2020 08:03:03 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 991BC386F82C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1589529783; bh=AqqCdymB+Wvw4yaiTDVoAKJuwZ40yhZxf/OZkmMy/h4=; h=From:To:Subject:Date:In-Reply-To:References:From; b=LYFXirSfwoQ0elvF6oLyi/pM83j5htM9B10AGxKEPE79g/KgHvY7T/4aUeja3ttQt xFIMqvK9qifWk0Iza72Vu1vd1Xi3z5vK1kdjHq3q+WsJeAvvq8E12xob+ViREvprPf TUk1oWRQJWu70RJY1+x0m+HKrBu2orhRxsqIdEDA= From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/95046] Vectorize V2SFmode operations Date: Fri, 15 May 2020 08:03:03 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 11.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: enhancement X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: ubizjak at gmail dot com X-Bugzilla-Target-Milestone: 11.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 May 2020 08:03:03 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D95046 --- Comment #12 from CVS Commits --- The master branch has been updated by Uros Bizjak : https://gcc.gnu.org/g:f8b0665445bee8673b62c0a40ae257fe8c75a9b6 commit r11-410-gf8b0665445bee8673b62c0a40ae257fe8c75a9b6 Author: Uros Bizjak Date: Fri May 15 10:02:00 2020 +0200 i386: Add V2SFmode hadd/hsub instructions [PR95046] PFACC/PFNACC 3dNow! instructions got their corresponding SSE alternative in SSE3, so these can't be implemented with TARGET_MMX_WITH_SSE, which implies SSE2. These instructions are only generated via builtins, and since several 3dNow! insns have no corresponding SSE alternative, we can't avoid MMX registers with 3dNow! builtins anyway. Add SSE3/AVX alternatives to the insn pattern, so compiler will be able to use XMM registers when available, but don't prevent MMX registers, since they are needed when SSE3 is not active. Add additional generic insn patterns, used by the combiner to synthesize horizontal V2SFmode add/sub instructions. These patterns are active for TARGET_MMX_WITH_SSE only, and use only XMM registers. gcc/ChangeLog: PR target/95046 * config/i386/i386.md (isa): Add sse3_noavx. (enabled): Handle sse3_noavx. * config/i386/mmx.md (mmx_haddv2sf3): New expander. (*mmx_haddv2sf3): Rename from mmx_haddv2sf3. Add SSE/AVX alternatives. Match commutative vec_select selector operands. (*mmx_haddv2sf3_low): New insn pattern. (*mmx_hsubv2sf3): Add SSE/AVX alternatives. (*mmx_hsubv2sf3_low): New insn pattern. testsuite/ChangeLog: PR target/95046 * gcc.target/i386/pr95046-8.c: New test.=