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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/95046] Vectorize V2SFmode operations
Date: Fri, 15 May 2020 07:25:23 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D95046

--- Comment #11 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:f4356120ba88c083dd5987376aab7590dd1e0e13

commit r11-409-gf4356120ba88c083dd5987376aab7590dd1e0e13
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Fri May 15 09:24:38 2020 +0200

    i386: Add V2SFmode hadd/hsub instructions [PR95046]

    PFACC/PFNACC 3dNow! instructions got their corresponding SSE alternative
    in SSE3, so these can't be implemented with TARGET_MMX_WITH_SSE, which
    implies SSE2.  These instructions are only generated via builtins, and
    since several 3dNow! insns have no corresponding SSE alternative,
    we can't avoid MMX registers with 3dNow! builtins anyway.

    Add SSE3/AVX alternatives to the insn pattern, so compiler will be able
    to use XMM registers when available, but don't prevent MMX registers,
    since they are needed when SSE3 is not active.

    Add additional generic insn patterns, used by the combiner to
    synthesize horizontal V2SFmode add/sub instructions.  These patterns
    are active for TARGET_MMX_WITH_SSE only, and use only XMM registers.

    gcc/ChangeLog:

            PR target/95046
            * config/i386/i386.md (isa): Add sse3_noavx.
            (enabled): Handle sse3_noavx.

            * config/i386/mmx.md (mmx_haddv2sf3): New expander.
            (*mmx_haddv2sf3): Rename from mmx_haddv2sf3.  Add SSE/AVX
            alternatives.  Match commutative vec_select selector operands.
            (*mmx_haddv2sf3_low): New insn pattern.

            (*mmx_hsubv2sf3): Add SSE/AVX alternatives.
            (*mmx_hsubv2sf3_low): New insn pattern.

    testsuite/ChangeLog:

            PR target/95046
            * gcc.target/i386/pr95046-8.c: New test.=