From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id C75D33851C27; Wed, 3 Jun 2020 09:51:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C75D33851C27 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1591177877; bh=J8lqLGmMaqpzwhI9NwtbUmp96us1GmVXUSCPgvqi6kI=; h=From:To:Subject:Date:In-Reply-To:References:From; b=THE4EUrPatMB5T2KmzsIzr0QSnkmaoNTLCX/k/tCmZYnbfR+pArn3Iuz7YN9hatTq zKEv6xxbespRi2fZ15fimVlXeCqW8A1WYJgighH8pohx8SQRcSOtSwjfp93qUntRYH Mh1uPeGPEcCwLFFCZbTU2gJOx5h5NQ2bzVaTxlS8= From: "rguenth at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/95493] [10/11 Regression] test for vector members apparently reordered with assignment to vector members since r10-7523-gb90061c6ec090c6b Date: Wed, 03 Jun 2020 09:51:17 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 10.1.0 X-Bugzilla-Keywords: alias, wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: rguenth at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 10.2 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: component Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 03 Jun 2020 09:51:17 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D95493 Richard Biener changed: What |Removed |Added ---------------------------------------------------------------------------- Component|middle-end |rtl-optimization --- Comment #3 from Richard Biener --- (In reply to Andrew Pinski from comment #2) > VIEW_CONVERT_EXPR(MEM[(struct SW &)&xx].d)[i.1_2] =3D -1; > _4 =3D MEM[(struct SW &)&xx].d; > y =3D _4; >=20 > There is some aliasing issues with the store and the next load. >=20 > THe tree level is correct, it goes wrong on the RTL level. ;; VIEW_CONVERT_EXPR(MEM[(struct SW &)&xx].d)[i.1_2] =3D -1; (insn 28 27 29 (set (reg:DI 92) (sign_extend:DI (reg:SI 83 [ i.1_2 ]))) "t.C":50:16 -1 (nil)) (insn 29 28 0 (set (mem/j:SI (plus:DI (plus:DI (mult:DI (reg:DI 92) (const_int 4 [0x4])) (reg/f:DI 77 virtual-stack-vars)) (const_int -32 [0xffffffffffffffe0])) [1 MEM[(struct ._anon= _0 *)_42] S4 A32]) (const_int -1 [0xffffffffffffffff])) "t.C":50:16 -1 (nil)) ;; y =3D _5; (insn 30 29 31 (set (reg:V4SI 93) (mem/c:V4SI (plus:DI (reg/f:DI 77 virtual-stack-vars) (const_int -32 [0xffffffffffffffe0])) [1 MEM[(struct SW &)_42].d+0 S16 A128])) -1 (nil)) (insn 31 30 0 (set (mem/c:V4SI (plus:DI (reg/f:DI 77 virtual-stack-vars) (const_int -16 [0xfffffffffffffff0])) [1 MEM[(vector(4) int *)_69]+0 S16 A128]) (reg:V4SI 93)) -1 (nil)) alias-sets look OK, the bases look sane as well. The only odd thing is that (anon *) which might confuse path-based analysis. PRE indeed decides that insn 29 does not affect the load in insn 30: deleting insn with uid =3D 30. PRE: redundant insn 30 (expression 3) in bb 4, reaching reg is 110 scanning new insn with uid =3D 146.=20 deleting insn with uid =3D 34. PRE: redundant insn 34 (expression 1) in bb 5, reaching reg is 111 PRE: edge (13,4), copy expression 1 PRE: edge (13,4), copy expression 3 PRE: store updated with reaching reg (reg:V4SI 110 [ MEM[(struct SW &)_42]= .d ]):=20 (insn 109 108 110 13 (set (mem/c:V4SI (plus:DI (reg/f:DI 19 frame) (const_int -32 [0xffffffffffffffe0])) [1 MEM[(struct SW *)_42].d+0 S16 A128]) (reg:V4SI 103)) "t.C":47:7 1347 {movv4si_internal} (expr_list:REG_DEAD (reg:V4SI 103) (nil))) > (In reply to Martin Li=C5=A1ka from comment #1) > > Confirmed, started with r10-7523-gb90061c6ec090c6b. >=20 > No just exposed.=