From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id A7648387084C; Wed, 17 Jun 2020 06:54:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A7648387084C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1592376893; bh=2WZK0auTHIEaxZjzkQhzpawgs001mkowqKANiDouElI=; h=From:To:Subject:Date:In-Reply-To:References:From; b=jbcc7GMg2avAwgUCqmMocqRbIvoFG3Hl0lZYJnvOReJtkMwweESnBkV39m91PLBnv MoRSrGbOhi0vKb8yaHZyjXW2rNZE+hP4tYaLGo5sv4CuCJDlKVgsrnjLsPKv9FPVUx FkaVWRGn4WmLeTHF+nUkPeIlhmOVRozYTQt3btL0= From: "rguenth at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/95713] [10/11 Regression] ICE in emit_move_insn when converting int2 vector to short2 vector for -march=skylake-avx512 since r10-5031-g78307657cf9675bc Date: Wed, 17 Jun 2020 06:54:53 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 10.1.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: rguenth at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 10.2 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cf_gcctarget target_milestone cc Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 17 Jun 2020 06:54:53 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D95713 Richard Biener changed: What |Removed |Added ---------------------------------------------------------------------------- Target|i?86-*-* |x86_64-*-* i?86-*-* Target Milestone|--- |10.2 CC| |hjl.tools at gmail dot com, | |kyukhin at gcc dot gnu.org --- Comment #2 from Richard Biener --- So the expansion of b_4 =3D VEC_PACK_TRUNC_EXPR <_2, _7>; with two V1SI operands results in a DImode rtx (reg:DI 93) but RTL expansion wants to see it in (reg:SI 84) (that is b). But the simplistic code doing that doesn't work (obviously): temp =3D force_operand (temp, target); if (temp !=3D target) emit_move_insn (target, temp); I guess the expansion of VEC_PACK_TRUNC_EXPR is "wrong". We do have CODE_FOR_vec_pack_trunc_si but that maps to (define_expand "vec_pack_trunc_" [(set (match_operand: 0 "register_operand") (ior: (ashift: (zero_extend: (match_operand:SWI24 2 "register_operand")) (match_dup 3)) (zero_extend: (match_operand:SWI24 1 "register_operand"))))] "TARGET_AVX512BW" where expand_binop_directly does 1098 if (binoptab =3D=3D vec_pack_trunc_optab ... 1106 /* The mode of the result is different then the mode of the 1107 arguments. */ 1108 tmp_mode =3D insn_data[(int) icode].operand[0].mode; and tmp_mode ends up as DImode. Shouldn't the pattern use HALFMASKMODE? Are those patterns supposed to only trigger for VECTOR_BOOLEAN and not "generic" vectors mapping to integer modes?=