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From: "rsandifo at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/95962] Inefficient code for simple arm_neon.h iota
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Date: Fri, 20 Aug 2021 11:52:08 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D95962

--- Comment #2 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.or=
g> ---
(In reply to Tamar Christina from comment #1)
> We generate the correct code at -O3 but not -O2.
>=20
> At -O3 we generate
>=20
> foo:
>         adrp    x0, .LC0
>         sub     sp, sp, #16
>         ldr     q0, [x0, #:lo12:.LC0]
>         add     sp, sp, 16
>         ret
>=20
> where the problem seems to be at at -O2 store merging has broken up the
> construction of `array` into two separate memory accesses:
>=20
>   MEM <unsigned long> [(int *)&array] =3D 4294967296;
>   MEM <unsigned long> [(int *)&array + 8B] =3D 12884901890;
>=20
> whereas at -O3 we still have a single assignment:
>=20
>   MEM <vector(4) int> [(int *)&array] =3D { 0, 1, 2, 3 };
>=20
> I'm not sure even if we made these loads gimple level if that would help.
> we'd still have the explicit MEMs created by store merging.
If we folded them to gimple loads, the gimple optimisers should replace
the MEM with an assignment of the VECTOR_CST { 0, 1, 2, 3 } to an SSA name,
with the function returning the SSA name.

expand will convert this back into a memory access, in the form of
an RTL constant pool load.  But that will avoid the stack temporary
and thus the pointless stack adjustments.=