[Bug tree-optimization/96226] New: Failure to optimize shift+not to rotate

[Bug tree-optimization/96226] New: Failure to optimize shift+not to rotate

[gabravier at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96226

            Bug ID: 96226
           Summary: Failure to optimize shift+not to rotate
           Product: gcc
           Version: 11.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: tree-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: gabravier at gmail dot com
  Target Milestone: ---

int32_t f(int32_t x)
{
    return ~(1 << (x & 0x1F));
}

This can be transformed to doing a rotate of -2 and x. This transformation is
done by LLVM, but not by GCC.

PS: GCC seems capable of doing this optimization, but only if `x & 0x1F` is
replaced with `x`, which either means that GCC is underoptimizing this or that
LLVM is somehow wrong.

[Bug tree-optimization/96226] Failure to optimize shift+not to rotate

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96226

--- Comment #1 from Uroš Bizjak <ubizjak at gmail dot com> ---
The combine produces:

Trying 7, 8 -> 9:
    7: r89:SI=0x1
    8: {r88:SI=r89:SI<<r90:SI&0x1f#0;clobber flags:CC;}
      REG_DEAD r90:SI
      REG_UNUSED flags:CC
      REG_DEAD r89:SI
    9: r86:SI=~r88:SI
      REG_DEAD r88:SI
Failed to match this instruction:
(set (reg:SI 86)
    (rotate:SI (const_int -2 [0xfffffffffffffffe])
        (subreg:QI (and:SI (reg:SI 90)
                (const_int 31 [0x1f])) 0)))
Successfully matched this instruction:
(set (reg:SI 88)
    (and:SI (reg:SI 90)
        (const_int 31 [0x1f])))
Failed to match this instruction:
(set (reg:SI 86)
    (rotate:SI (const_int -2 [0xfffffffffffffffe])
        (subreg:QI (reg:SI 88) 0)))
starting the processing of deferred insns
rescanning insn with uid = 8.
ending the processing of deferred insns

which tries to match:

(define_insn_and_split "*<rotate_insn><mode>3_mask"
  [(set (match_operand:SWI48 0 "nonimmediate_operand")
        (any_rotate:SWI48
          (match_operand:SWI48 1 "nonimmediate_operand")
          (subreg:QI
            (and:SI
              (match_operand:SI 2 "register_operand" "c")
              (match_operand:SI 3 "const_int_operand")) 0)))
   (clobber (reg:CC FLAGS_REG))]
  "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
   && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
      == GET_MODE_BITSIZE (<MODE>mode)-1

However, the above pattern doesn't allow immediate operand.

[Bug tree-optimization/96226] Failure to optimize shift+not to rotate

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96226

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jakub at gcc dot gnu.org

--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Created attachment 49683
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49683&action=edit
gcc11-pr96226.patch

Untested fix.

[Bug tree-optimization/96226] Failure to optimize shift+not to rotate

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96226

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:ac2a6962b91128e700ee52db686dcdb2bab93790

commit r11-5747-gac2a6962b91128e700ee52db686dcdb2bab93790
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Fri Dec 4 18:44:31 2020 +0100

    i386: Add combine splitters to allow combining multiple insns into reg1 =
const; reg2 = rotate (reg1, reg3 & cst) [PR96226]

    As mentioned in the PR, we can combine ~(1 << x) into -2 r<< x, but we give
    up in the ~(1 << (x & 31)) cases, as *<rotate_insn><mode>3_mask* don't
allow
    immediate operand 1 and find_split_point prefers to split (x & 31) instead
    of the constant.

    With these combine splitters we help combine decide how to split those
    insns.

    2020-12-04  Jakub Jelinek  <jakub@redhat.com>

            PR target/96226
            * config/i386/i386.md (splitter after *<rotate_insn><mode>3_mask,
            splitter after *<rotate_insn><mode>3_mask_1): New combine
splitters.

            * gcc.target/i386/pr96226.c: New test.

[Bug tree-optimization/96226] Failure to optimize shift+not to rotate

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96226

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|UNCONFIRMED                 |RESOLVED

--- Comment #4 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Fixed for GCC 11+.

[Bug tree-optimization/96226] Failure to optimize shift+not to rotate

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96226

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:625e002396f7d0108f845bfba6a6f4f4fcadad05

commit r11-5756-g625e002396f7d0108f845bfba6a6f4f4fcadad05
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sat Dec 5 01:31:08 2020 +0100

    i386: Combine splitters followup [PR96226]

    Here is the patch to simplify the newly added combine splitters,
    when we split into 2 insns anyway, no reason to split into the masking
    define_insn_and_split we'd be splitting shortly after.

    2020-12-05  Jakub Jelinek  <jakub@redhat.com>

            PR target/96226
            * config/i386/i386.md (splitter after *<rotate_insn><mode>3_mask,
            splitter after *<rotate_insn><mode>3_mask_1): Drop the masking from
            the patterns to split into.