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From: "rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/96263] [10/11 Regression] ICE: in lra_assign, at
 lra-assigns.c:1648 with -O -flive-range-shrinkage -fnon-call-exceptions
 -msse4 --param=max-sched-ready-insns=1 since r10-4373-gc265dfbf748e9fc3
Date: Thu, 23 Jul 2020 11:17:03 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D96263

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |missed-optimization

--- Comment #3 from Richard Biener <rguenth at gcc dot gnu.org> ---
veclower, esp. VEC_COND_EXPR lowering certainly makes a mess out of the
testcase
(doing component-wise rather than smaller-vector size operations).  Also
somehow doing odd things like

  _5 =3D {e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.=
4_6, e
.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6,
e.4_
6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.=
4_6,=20
e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6,
e.4
_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6,
e.4_6,
 e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6};
   f.68_7 =3D f;
-  r_74 =3D _5 & f.68_7;
+  _35 =3D {e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, =
e.4_6,=20
e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6,
e.4
_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6,
e.4_6,
 e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_=
6,
e.
4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6,
e.4_6
, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6};
+  _38 =3D BIT_FIELD_REF <_35, 128, 0>;
+  _40 =3D BIT_FIELD_REF <f.68_7, 128, 0>;
+  _43 =3D _38 & _40;
+  _45 =3D {e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, =
e.4_6,=20
e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6,
e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6,
e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6,
e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6,
e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6, e.4_6};
+  _85 =3D BIT_FIELD_REF <_45, 128, 128>;
+  _56 =3D BIT_FIELD_REF <f.68_7, 128, 128>;
+  _61 =3D _56 & _85;
...

that _35 is v64qi.  Eventually the removed folding made a smaller CTOR from=
 it,
but re-emitting the CTOR makes no sense at all.  Luckily we clean that up
(I have no hopes for -O0 though).  We should make veclower behave more
sanely.

But the change probably just exposed a latent bug.=