[Bug tree-optimization/96270] [8/9/10/11 Regression] stdarg malfunction with -m32 and -Os

["rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96270

--- Comment #4 from Richard Biener <rguenth at gcc dot gnu.org> ---
Note the complication is that u.r is of type 'double' and thus DFmode
which has a mode precision of 64.  So this is once again the x86 backend
using float loads/stores that are value-changing (IIRC the ABI specifies
passing 'double' as long double.

So the IL "lies" here and "fixing" this would pessimize targets that do not
lie for no good reason.

(insn 13 12 14 4 (set (mem:DI (pre_dec:SI (reg/f:SI 7 sp)) [0  S8 A64])
        (subreg:DI (reg:DF 84 [ pretmp_11 ]) 0)) "t.c":21:5 50 {*pushdi2}
     (expr_list:REG_ARGS_SIZE (const_int 12 [0xc])
        (nil)))

(what's this REG_ARGS_SIZE?)

eventually gets after LRA

(insn 35 6 7 2 (set (mem/c:DF (plus:SI (reg/f:SI 6 bp)
                (const_int -16 [0xfffffffffffffff0])) [7 %sfp+-8 S8 A64])
        (reg:DF 8 st [orig:84 pretmp_11 ] [84])) "t.c":21:5 135
{*movdf_internal}
     (nil))
...

(insn 13 12 14 3 (set (mem:DI (pre_dec:SI (reg/f:SI 7 sp)) [0  S8 A64])
        (mem/c:DI (plus:SI (reg/f:SI 6 bp)
                (const_int -16 [0xfffffffffffffff0])) [7 %sfp+-8 S8 A64]))
"t.c":21:5 50 {*pushdi2}

clearly inheritance could somehow have picked up

(insn 6 3 35 2 (set (reg:DF 8 st [orig:84 pretmp_11 ] [84])
        (mem/j:DF (reg/v/f:SI 0 ax [orig:86 p ] [86]) [4 p_6(D)->u.r+0 S8
A32])) "t.c":21:5 135 {*movdf_internal}
     (nil))

instead but it really looks like the targets fault.

It's unfortunately not possible to fix the code hoisting side without
also pessimizing valid CSE where desirable.  Maybe we need a new target
hook like targetm.can_ldst_unaltered_bits (machine_mode) and x86
has to say no for all x87 modes but long double?  It also means that
spilling would alter values (but IIRC we always _spill_ via long double).