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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug c/96683] Arm: MVE ACLE intrinsics vst1q_{s8|u8|s16|u16} is not
 supported by GCC.
Date: Thu, 20 Aug 2020 15:27:23 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D96683

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Joe Ramsay <joeramsay@gcc.gnu.org>:

https://gcc.gnu.org/g:91d206adfe39ce063f6a5731b92a03c05e82e94a

commit r11-2782-g91d206adfe39ce063f6a5731b92a03c05e82e94a
Author: Joe Ramsay <Joe.Ramsay@arm.com>
Date:   Wed Aug 19 12:34:06 2020 +0000

    arm: Require MVE memory operand for destination of vst1q intrinsic

    Previously, the machine description patterns for vst1q accepted a gener=
ic
memory
    operand for the destination, which could lead to an unrecognised builtin
when
    expanding vst1q* intrinsics. This change fixes the pattern to only acce=
pt
MVE
    memory operands.

    gcc/ChangeLog:

            PR target/96683
            * config/arm/mve.md (mve_vst1q_f<mode>): Require MVE memory ope=
rand
for
            destination.
            (mve_vst1q_<supf><mode>): Likewise.

    gcc/testsuite/ChangeLog:

            PR target/96683
            * gcc.target/arm/mve/intrinsics/vst1q_f16.c: New test.
            * gcc.target/arm/mve/intrinsics/vst1q_s16.c: New test.
            * gcc.target/arm/mve/intrinsics/vst1q_s8.c: New test.
            * gcc.target/arm/mve/intrinsics/vst1q_u16.c: New test.
            * gcc.target/arm/mve/intrinsics/vst1q_u8.c: New test.=