* [Bug target/96744] [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test
2020-08-22 12:28 [Bug target/96744] New: [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test hjl.tools at gmail dot com
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From: cvs-commit at gcc dot gnu.org @ 2020-08-23 15:40 UTC (permalink / raw)
To: gcc-bugs
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--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by H.J. Lu <hjl@gcc.gnu.org>:
https://gcc.gnu.org/g:87c753ac241f25d222d46ba1ac66ceba89d6a200
commit r11-2812-g87c753ac241f25d222d46ba1ac66ceba89d6a200
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Fri Aug 21 09:42:49 2020 -0700
x86: Add target("general-regs-only") function attribute
gcc/
PR target/96744
* config/i386/i386-options.c (IX86_ATTR_IX86_YES): New.
(IX86_ATTR_IX86_NO): Likewise.
(ix86_opt_type): Add ix86_opt_ix86_yes and ix86_opt_ix86_no.
(ix86_valid_target_attribute_inner_p): Handle general-regs-only,
ix86_opt_ix86_yes and ix86_opt_ix86_no.
(ix86_option_override_internal): Check opts->x_ix86_target_flags
instead of opts->x_ix86_target_flags.
* doc/extend.texi: Document target("general-regs-only") function
attribute.
gcc/testsuite/
PR target/96744
* gcc.target/i386/pr96744-1.c: New test.
* gcc.target/i386/pr96744-2.c: Likewise.
* gcc.target/i386/pr96744-3a.c: Likewise.
* gcc.target/i386/pr96744-3b.c: Likewise.
* gcc.target/i386/pr96744-4.c: Likewise.
* gcc.target/i386/pr96744-5.c: Likewise.
* gcc.target/i386/pr96744-6.c: Likewise.
* gcc.target/i386/pr96744-7.c: Likewise.
* gcc.target/i386/pr96744-8a.c: Likewise.
* gcc.target/i386/pr96744-8b.c: Likewise.
* gcc.target/i386/pr96744-9.c: Likewise.
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug target/96744] [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test
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To: gcc-bugs
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--- Comment #2 from Hongtao.liu <crazylht at gmail dot com> ---
Created attachment 49107
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49107&action=edit
Enable spill to mask only under m_core_AVX512
this patch will fail
cat test.c
----
#include<immintrin.h>
void
_mm512_2intersect_epi32_cut (__m512i __A, __m512i __B, __mmask16 *__U,
__mmask16 *__M)
{
__builtin_ia32_2intersectd512 (__U, __M, (__v16si) __A, (__v16si) __B);
}
void
_mm512_2intersect_epi64_cut (__m512i __A, __m512i __B, __mmask8 *__U,
__mmask8 *__M)
{
__builtin_ia32_2intersectq512 (__U, __M, (__v8di) __A, (__v8di) __B);
}
---
with gcc -O2 -mavx512vp2intersect -mavx512bw -mavx512dq
during RTL pass: reload
dump file: avx-1_cut.c.287r.reload
avx-1_cut.c: In function ‘_mm512_2intersect_epi32_cut’:
avx-1_cut.c:7:1: internal compiler error: in emit_move_multi_word, at
expr.c:3680
7 | }
| ^
0xd59c56 emit_move_multi_word
/export/users2/liuhongt/gcc/gnu-toolchain/tune_spill_to_mask/gcc/expr.c:3680
0xd5a2e3 emit_move_insn_1(rtx_def*, rtx_def*)
/export/users2/liuhongt/gcc/gnu-toolchain/tune_spill_to_mask/gcc/expr.c:3802
0xd5ab32 emit_move_insn(rtx_def*, rtx_def*)
/export/users2/liuhongt/gcc/gnu-toolchain/tune_spill_to_mask/gcc/expr.c:3935
0x1024e79 lra_emit_move(rtx_def*, rtx_def*)
/export/users2/liuhongt/gcc/gnu-toolchain/tune_spill_to_mask/gcc/lra.c:502
0x1043bb3 curr_insn_transform
/export/users2/liuhongt/gcc/gnu-toolchain/tune_spill_to_mask/gcc/lra-constraints.c:4440
0x10459d4 lra_constraints(bool)
/export/users2/liuhongt/gcc/gnu-toolchain/tune_spill_to_mask/gcc/lra-constraints.c:5031
0x1029896 lra(_IO_FILE*)
/export/users2/liuhongt/gcc/gnu-toolchain/tune_spill_to_mask/gcc/lra.c:2415
0xfba828 do_reload
/export/users2/liuhongt/gcc/gnu-toolchain/tune_spill_to_mask/gcc/ira.c:5525
0xfbad1e execute
/export/users2/liuhongt/gcc/gnu-toolchain/tune_spill_to_mask/gcc/ira.c:5711
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
Need to add define_insn for movp2qi/movp2hi?
with -mavx512vp2intersect -mavx512bw -mavx512dq -m32 got different failure
message.
avx-1_cut.c: In function ‘_mm512_2intersect_epi32_cut’:
avx-1_cut.c:7:1: internal compiler error: maximum number of generated reload
insns per insn achieved (90)
7 | }
| ^
0x1045568 lra_constraints(bool)
/export/users2/liuhongt/gcc/gnu-toolchain/tune_spill_to_mask/gcc/lra-constraints.c:4954
0x1029896 lra(_IO_FILE*)
/export/users2/liuhongt/gcc/gnu-toolchain/tune_spill_to_mask/gcc/lra.c:2415
0xfba828 do_reload
/export/users2/liuhongt/gcc/gnu-toolchain/tune_spill_to_mask/gcc/ira.c:5525
0xfbad1e execute
/export/users2/liuhongt/gcc/gnu-toolchain/tune_spill_to_mask/gcc/ira.c:5711
Please submit a full bug report,
Not sure about this one.
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug target/96744] [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test
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To: gcc-bugs
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--- Comment #3 from Uroš Bizjak <ubizjak at gmail dot com> ---
Created attachment 49112
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49112&action=edit
Retune mask <-> general moves cost
It looks to me that mask <-> general cost is too low, so the compiler now
prefers these moves too much. Attached patch equalizes mask <-> general cost
with xmm <-> general cost, and it seems to fix the problem.
Hongjiu, can you please retune the costs, using the attached patch as the
start?
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug target/96744] [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test
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--- Comment #4 from Uroš Bizjak <ubizjak at gmail dot com> ---
Created attachment 49114
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49114&action=edit
Double-reg mask moves
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug target/96744] [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test
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--- Comment #5 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Hongtao.liu from comment #2)
> Need to add define_insn for movp2qi/movp2hi?
Yes, this is needed to cover some corner cases. Please see attachment 49114.
However, the patch assumes that avx512vp2intersect implies mavx512dq, otherwise
there is no direct QImode move from mask register to memory available.
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug target/96744] [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test
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--- Comment #6 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Uroš Bizjak from comment #5)
> However, the patch assumes that avx512vp2intersect implies mavx512dq,
> otherwise there is no direct QImode move from mask register to memory
> available.
This is the testcase:
--cut here--
typedef unsigned char __mmask8;
typedef unsigned short __mmask16;
typedef long long __m512i __attribute__ ((__vector_size__ (64),
__may_alias__));
typedef int __v16si __attribute__ ((__vector_size__ (64)));
typedef long long __v8di __attribute__ ((__vector_size__ (64)));
void
_mm512_2intersect_epi64 (__m512i __A, __m512i __B, __mmask8 *__U,
__mmask8 *__M)
{
__builtin_ia32_2intersectq512 (__U, __M, (__v8di) __A, (__v8di) __B);
}
--cut here--
cc1 -O2 -march=k8 -mavx512vp2intersect -mavx512bw pr96744.c
pr96744.c:13:1: error: insn does not satisfy its constraints:
13 | }
| ^
(insn 24 9 25 2 (set (mem/c:QI (plus:DI (reg/f:DI 7 sp)
(const_int -2 [0xfffffffffffffffe])) [1 %sfp+-2 S1 A16])
(reg:QI 68 k0 [86])) "pr96744.c":12:3 77 {*movqi_internal}
(expr_list:REG_DEAD (reg:QI 68 k0 [86])
(nil)))
during RTL pass: cprop_hardreg
compiles OK when -mavx512dq is added.
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug target/96744] [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test
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From: crazylht at gmail dot com @ 2020-08-25 5:14 UTC (permalink / raw)
To: gcc-bugs
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--- Comment #7 from Hongtao.liu <crazylht at gmail dot com> ---
(In reply to Uroš Bizjak from comment #5)
> (In reply to Hongtao.liu from comment #2)
>
> > Need to add define_insn for movp2qi/movp2hi?
>
> Yes, this is needed to cover some corner cases. Please see attachment 49114
> [details].
>
> However, the patch assumes that avx512vp2intersect implies mavx512dq,
Let me check this part.
> otherwise there is no direct QImode move from mask register to memory
> available.
and QImode masks would be indirectly stored through Q_REG.
cut from ix86_secondary_reload
---
/* QImode spills from non-QI registers require
intermediate register on 32bit targets. */
if (mode == QImode
&& ((!TARGET_64BIT && !in_p
&& INTEGER_CLASS_P (rclass)
&& MAYBE_NON_Q_CLASS_P (rclass))
|| (!TARGET_AVX512DQ
&& MAYBE_MASK_CLASS_P (rclass))))
{
int regno = true_regnum (x);
/* Return Q_REGS if the operand is in memory. */
if (regno == -1)
return Q_REGS;
return NO_REGS;
---
if we disable direct movement between gpr and masks in
inline_secondary_memory_needed, how should pass_reload spill QImode mask to
memeory, would it be functionality issue?
That's why i prefer changing cost model to disable spill to mask in general
target, as your patch "Retune mask <-> general moves cost" shows: attachment
49107
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug target/96744] [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test
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From: rguenth at gcc dot gnu.org @ 2020-08-25 11:38 UTC (permalink / raw)
To: gcc-bugs
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Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Ever confirmed|0 |1
Last reconfirmed| |2020-08-25
Version|10.2.1 |11.0
Target Milestone|--- |11.0
Status|UNCONFIRMED |NEW
--- Comment #8 from Richard Biener <rguenth at gcc dot gnu.org> ---
Confirmed.
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug target/96744] [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test
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To: gcc-bugs
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--- Comment #9 from Hongtao.liu <crazylht at gmail dot com> ---
(In reply to Hongtao.liu from comment #7)
> (In reply to Uroš Bizjak from comment #5)
> > (In reply to Hongtao.liu from comment #2)
> >
> > > Need to add define_insn for movp2qi/movp2hi?
> >
> > Yes, this is needed to cover some corner cases. Please see attachment 49114 [details]
> > [details].
> >
> > However, the patch assumes that avx512vp2intersect implies mavx512dq,
>
> Let me check this part.
Confirmed, avx512vp2intersect implies avx512dq.
Should bellow in the same patch with attachment 49114, or a separate patch?
---
diff --git a/gcc/common/config/i386/i386-common.c
b/gcc/common/config/i386/i386-common.c
index bb14305ad7b..5305145a8c9 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -906,8 +906,8 @@ ix86_handle_option (struct gcc_options *opts,
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
opts->x_ix86_isa_flags2_explicit |=
OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
- opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
- opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
}
else
{
---
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug target/96744] [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test
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To: gcc-bugs
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--- Comment #10 from Hongtao.liu <crazylht at gmail dot com> ---
(In reply to Uroš Bizjak from comment #3)
> Created attachment 49112 [details]
> Retune mask <-> general moves cost
>
> It looks to me that mask <-> general cost is too low, so the compiler now
> prefers these moves too much. Attached patch equalizes mask <-> general cost
> with xmm <-> general cost, and it seems to fix the problem.
>
> Hongjiu, can you please retune the costs, using the attached patch as the
> start?
I'll spend some time to retune it.
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug target/96744] [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test
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From: ubizjak at gmail dot com @ 2020-08-27 11:09 UTC (permalink / raw)
To: gcc-bugs
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--- Comment #11 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Hongtao.liu from comment #9)
> > > However, the patch assumes that avx512vp2intersect implies mavx512dq,
> >
> > Let me check this part.
>
> Confirmed, avx512vp2intersect implies avx512dq.
>
> Should bellow in the same patch with attachment 49114 [details], or a
> separate patch?
Please commit this patch first (the patch is pre-approved), followed by
attachment 49119 (which is also pre-approved as a separate patch) after they
pass standard bootstrap/regression test cycle.
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug target/96744] [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test
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--- Comment #12 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:
https://gcc.gnu.org/g:58d6eea0e0754351b399a4b85562f81326a184ad
commit r11-2917-g58d6eea0e0754351b399a4b85562f81326a184ad
Author: liuhongt <hongtao.liu@intel.com>
Date: Wed Aug 26 15:24:10 2020 +0800
Add expander for movp2hi and movp2qi.
2020-08-30 Uros Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
PR target/96744
* config/i386/i386-expand.c (split_double_mode): Also handle
E_P2HImode and E_P2QImode.
* config/i386/sse.md (MASK_DWI): New define_mode_iterator.
(mov<mode>): New expander for P2HI,P2QI.
(*mov<mode>_internal): New define_insn_and_split to split
movement of P2QI/P2HI to 2 movqi/movhi patterns after reload.
gcc/testsuite/ChangeLog:
* gcc.target/i386/double_mask_reg-1.c: New test.
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug target/96744] [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test
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--- Comment #13 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by hongtao Liu
<liuhongt@gcc.gnu.org>:
https://gcc.gnu.org/g:436ee9fec2751826bc48069d4dd320207fd9dfa4
commit r10-8684-g436ee9fec2751826bc48069d4dd320207fd9dfa4
Author: liuhongt <hongtao.liu@intel.com>
Date: Wed Aug 26 15:24:10 2020 +0800
Add expander for movp2hi and movp2qi.
2020-08-30 Uros Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
PR target/96744
* config/i386/i386-expand.c (split_double_mode): Also handle
E_P2HImode and E_P2QImode.
* config/i386/sse.md (MASK_DWI): New define_mode_iterator.
(mov<mode>): New expander for P2HI,P2QI.
(*mov<mode>_internal): New define_insn_and_split to split
movement of P2QI/P2HI to 2 movqi/movhi patterns after reload.
gcc/testsuite/ChangeLog:
* gcc.target/i386/double_mask_reg-1.c: New test.
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug target/96744] [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test
2020-08-22 12:28 [Bug target/96744] New: [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test hjl.tools at gmail dot com
` (12 preceding siblings ...)
2020-08-28 7:53 ` cvs-commit at gcc dot gnu.org
@ 2020-09-15 10:23 ` cvs-commit at gcc dot gnu.org
2020-09-15 10:24 ` crazylht at gmail dot com
2020-10-12 12:28 ` rguenth at gcc dot gnu.org
15 siblings, 0 replies; 17+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2020-09-15 10:23 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96744
--- Comment #14 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:
https://gcc.gnu.org/g:ecc3135a4a264b66c163ef32e815a99746b81800
commit r11-3202-gecc3135a4a264b66c163ef32e815a99746b81800
Author: liuhongt <hongtao.liu@intel.com>
Date: Mon Aug 24 20:36:52 2020 +0800
Retune mask <->integer cost for non-AVX512 micro-architecture.
gcc/ChangeLog:
PR target/96744
* config/i386/x86-tune-costs.h (struct processor_costs):
Increase mask <-> integer cost for non AVX512 target to avoid
spill gpr to mask. Also retune mask <-> integer and
mask_load/store for skylake_cost.
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug target/96744] [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test
2020-08-22 12:28 [Bug target/96744] New: [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test hjl.tools at gmail dot com
` (13 preceding siblings ...)
2020-09-15 10:23 ` cvs-commit at gcc dot gnu.org
@ 2020-09-15 10:24 ` crazylht at gmail dot com
2020-10-12 12:28 ` rguenth at gcc dot gnu.org
15 siblings, 0 replies; 17+ messages in thread
From: crazylht at gmail dot com @ 2020-09-15 10:24 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96744
--- Comment #15 from Hongtao.liu <crazylht at gmail dot com> ---
Fixed in GCC11.
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug target/96744] [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test
2020-08-22 12:28 [Bug target/96744] New: [11 Regression] FAIL: gcc.target/i386/avx512bitalgvl-vpopcntb-1.c execution test hjl.tools at gmail dot com
` (14 preceding siblings ...)
2020-09-15 10:24 ` crazylht at gmail dot com
@ 2020-10-12 12:28 ` rguenth at gcc dot gnu.org
15 siblings, 0 replies; 17+ messages in thread
From: rguenth at gcc dot gnu.org @ 2020-10-12 12:28 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96744
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Status|NEW |RESOLVED
--- Comment #16 from Richard Biener <rguenth at gcc dot gnu.org> ---
fixed.
^ permalink raw reply [flat|nested] 17+ messages in thread