* [Bug target/96759] ICE in extract_insn, at recog.c:2294
2020-08-24 7:41 [Bug target/96759] New: ICE in extract_insn, at recog.c:2294 marxin at gcc dot gnu.org
@ 2020-08-24 8:52 ` kito at gcc dot gnu.org
2020-09-02 9:08 ` kito at gcc dot gnu.org
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: kito at gcc dot gnu.org @ 2020-08-24 8:52 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96759
Kito Cheng <kito at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Ever confirmed|0 |1
Status|UNCONFIRMED |NEW
Last reconfirmed| |2020-08-24
--- Comment #1 from Kito Cheng <kito at gcc dot gnu.org> ---
Confirmed
^ permalink raw reply [flat|nested] 9+ messages in thread* [Bug target/96759] ICE in extract_insn, at recog.c:2294
2020-08-24 7:41 [Bug target/96759] New: ICE in extract_insn, at recog.c:2294 marxin at gcc dot gnu.org
2020-08-24 8:52 ` [Bug target/96759] " kito at gcc dot gnu.org
@ 2020-09-02 9:08 ` kito at gcc dot gnu.org
2020-09-03 6:30 ` [Bug target/96759] [10/11 Regression] " kito at gcc dot gnu.org
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: kito at gcc dot gnu.org @ 2020-09-02 9:08 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96759
--- Comment #2 from Kito Cheng <kito at gcc dot gnu.org> ---
It work on GCC 9, GCC will split that into two plain move instead of move from
a (subreg (parallel [(reg) (reg)])).
(insn 23 22 24 (set (reg:SI 83)
(reg:SI 10 a0)) "g++.target/riscv/pr96759.C":8:38 -1
(nil))
(insn 24 23 25 (set (reg:DF 84)
(reg:DF 42 fa0)) "g++.target/riscv/pr96759.C":8:38 -1
(nil))
But it will ICE after GCC 10, try to bisect to figure out the reason.
^ permalink raw reply [flat|nested] 9+ messages in thread* [Bug target/96759] [10/11 Regression] ICE in extract_insn, at recog.c:2294
2020-08-24 7:41 [Bug target/96759] New: ICE in extract_insn, at recog.c:2294 marxin at gcc dot gnu.org
2020-08-24 8:52 ` [Bug target/96759] " kito at gcc dot gnu.org
2020-09-02 9:08 ` kito at gcc dot gnu.org
@ 2020-09-03 6:30 ` kito at gcc dot gnu.org
2020-10-14 3:55 ` cvs-commit at gcc dot gnu.org
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: kito at gcc dot gnu.org @ 2020-09-03 6:30 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96759
--- Comment #3 from Kito Cheng <kito at gcc dot gnu.org> ---
ICE after g:70cdb21e579191fe9f0f1d45e328908e59c0179e
^ permalink raw reply [flat|nested] 9+ messages in thread* [Bug target/96759] [10/11 Regression] ICE in extract_insn, at recog.c:2294
2020-08-24 7:41 [Bug target/96759] New: ICE in extract_insn, at recog.c:2294 marxin at gcc dot gnu.org
` (2 preceding siblings ...)
2020-09-03 6:30 ` [Bug target/96759] [10/11 Regression] " kito at gcc dot gnu.org
@ 2020-10-14 3:55 ` cvs-commit at gcc dot gnu.org
2020-10-14 14:54 ` kito at gcc dot gnu.org
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2020-10-14 3:55 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96759
--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kito Cheng <kito@gcc.gnu.org>:
https://gcc.gnu.org/g:78fbe731a8822e819c4ca0e6d6f777c7a2f36bad
commit r11-3860-g78fbe731a8822e819c4ca0e6d6f777c7a2f36bad
Author: Kito Cheng <kito.cheng@sifive.com>
Date: Wed Sep 2 14:26:15 2020 +0800
PR target/96759 - Handle global variable assignment from misaligned
structure/PARALLEL return values.
In g:70cdb21e579191fe9f0f1d45e328908e59c0179e, DECL/global variable has
handled
misaligned stores, but it didn't handle PARALLEL values, and I refer the
other part of this function, I found the PARALLEL need handled by
emit_group_* functions, so I add a check, and using emit_group_store if
storing a PARALLEL value, also checked this change didn't break the
testcase(gcc.target/arm/unaligned-argument-3.c) added by the orginal
changes.
For riscv64 target, struct S {int a; double b;} will pack into a parallel
value to return and it has TImode when misaligned access is supported,
however TImode required 16-byte align, but it only 8-byte align, so it go
to
the misaligned stores handling, then it will try to generate move
instruction from a PARALLEL value.
Tested on following target without introduced new reguression:
- riscv32/riscv64 elf
- x86_64-linux
- arm-eabi
v2 changes:
- Use maybe_emit_group_store instead of emit_group_store.
- Remove push_temp_slots/pop_temp_slots, emit_group_store only require
stack temp slot when dst is CONCAT or PARALLEL, however
maybe_emit_group_store will always use REG for dst if needed.
gcc/ChangeLog:
PR target/96759
* expr.c (expand_assignment): Handle misaligned stores with
PARALLEL
value.
gcc/testsuite/ChangeLog:
PR target/96759
* g++.target/riscv/pr96759.C: New.
* gcc.target/riscv/pr96759.c: New.
^ permalink raw reply [flat|nested] 9+ messages in thread* [Bug target/96759] [10/11 Regression] ICE in extract_insn, at recog.c:2294
2020-08-24 7:41 [Bug target/96759] New: ICE in extract_insn, at recog.c:2294 marxin at gcc dot gnu.org
` (3 preceding siblings ...)
2020-10-14 3:55 ` cvs-commit at gcc dot gnu.org
@ 2020-10-14 14:54 ` kito at gcc dot gnu.org
2020-10-16 12:19 ` rguenth at gcc dot gnu.org
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: kito at gcc dot gnu.org @ 2020-10-14 14:54 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96759
Kito Cheng <kito at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Assignee|unassigned at gcc dot gnu.org |kito at gcc dot gnu.org
Status|NEW |ASSIGNED
--- Comment #5 from Kito Cheng <kito at gcc dot gnu.org> ---
Committed to trunk, will set as resolve after commit to gcc 10 branch :)
^ permalink raw reply [flat|nested] 9+ messages in thread* [Bug target/96759] [10/11 Regression] ICE in extract_insn, at recog.c:2294
2020-08-24 7:41 [Bug target/96759] New: ICE in extract_insn, at recog.c:2294 marxin at gcc dot gnu.org
` (4 preceding siblings ...)
2020-10-14 14:54 ` kito at gcc dot gnu.org
@ 2020-10-16 12:19 ` rguenth at gcc dot gnu.org
2020-10-22 8:38 ` cvs-commit at gcc dot gnu.org
2020-10-22 9:18 ` kito at gcc dot gnu.org
7 siblings, 0 replies; 9+ messages in thread
From: rguenth at gcc dot gnu.org @ 2020-10-16 12:19 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96759
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Target Milestone|--- |10.3
^ permalink raw reply [flat|nested] 9+ messages in thread* [Bug target/96759] [10/11 Regression] ICE in extract_insn, at recog.c:2294
2020-08-24 7:41 [Bug target/96759] New: ICE in extract_insn, at recog.c:2294 marxin at gcc dot gnu.org
` (5 preceding siblings ...)
2020-10-16 12:19 ` rguenth at gcc dot gnu.org
@ 2020-10-22 8:38 ` cvs-commit at gcc dot gnu.org
2020-10-22 9:18 ` kito at gcc dot gnu.org
7 siblings, 0 replies; 9+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2020-10-22 8:38 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96759
--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Kito Cheng <kito@gcc.gnu.org>:
https://gcc.gnu.org/g:3444bed1a0bedf8c5e97ba9b0de6a547bb375ead
commit r10-8936-g3444bed1a0bedf8c5e97ba9b0de6a547bb375ead
Author: Kito Cheng <kito.cheng@sifive.com>
Date: Wed Sep 2 14:26:15 2020 +0800
PR target/96759 - Handle global variable assignment from misaligned
structure/PARALLEL return values.
In g:70cdb21e579191fe9f0f1d45e328908e59c0179e, DECL/global variable has
handled
misaligned stores, but it didn't handle PARALLEL values, and I refer the
other part of this function, I found the PARALLEL need handled by
emit_group_* functions, so I add a check, and using emit_group_store if
storing a PARALLEL value, also checked this change didn't break the
testcase(gcc.target/arm/unaligned-argument-3.c) added by the orginal
changes.
For riscv64 target, struct S {int a; double b;} will pack into a parallel
value to return and it has TImode when misaligned access is supported,
however TImode required 16-byte align, but it only 8-byte align, so it go
to
the misaligned stores handling, then it will try to generate move
instruction from a PARALLEL value.
Tested on following target without introduced new reguression:
- riscv32/riscv64 elf
- x86_64-linux
- arm-eabi
v2 changes:
- Use maybe_emit_group_store instead of emit_group_store.
- Remove push_temp_slots/pop_temp_slots, emit_group_store only require
stack temp slot when dst is CONCAT or PARALLEL, however
maybe_emit_group_store will always use REG for dst if needed.
gcc/ChangeLog:
PR target/96759
* expr.c (expand_assignment): Handle misaligned stores with
PARALLEL
value.
gcc/testsuite/ChangeLog:
PR target/96759
* g++.target/riscv/pr96759.C: New.
* gcc.target/riscv/pr96759.c: New.
(cherry picked from commit 78fbe731a8822e819c4ca0e6d6f777c7a2f36bad)
^ permalink raw reply [flat|nested] 9+ messages in thread* [Bug target/96759] [10/11 Regression] ICE in extract_insn, at recog.c:2294
2020-08-24 7:41 [Bug target/96759] New: ICE in extract_insn, at recog.c:2294 marxin at gcc dot gnu.org
` (6 preceding siblings ...)
2020-10-22 8:38 ` cvs-commit at gcc dot gnu.org
@ 2020-10-22 9:18 ` kito at gcc dot gnu.org
7 siblings, 0 replies; 9+ messages in thread
From: kito at gcc dot gnu.org @ 2020-10-22 9:18 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96759
Kito Cheng <kito at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|ASSIGNED |RESOLVED
Resolution|--- |FIXED
--- Comment #7 from Kito Cheng <kito at gcc dot gnu.org> ---
Fixed on both trunk and gcc 10.
^ permalink raw reply [flat|nested] 9+ messages in thread