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From: "glisse at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/96918] Failure to optimize vector shift left+shift right+or to pshuf
Date: Thu, 03 Sep 2020 20:41:12 +0000	[thread overview]
Message-ID: <bug-96918-4-nIKYtC99x6@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-96918-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96918

--- Comment #5 from Marc Glisse <glisse at gcc dot gnu.org> ---
typedef unsigned short v8i16 __attribute__((vector_size(16)));

v8i16 bswap_epi16(v8i16 x)
{
        return (x << 8) | (x >> 8);
}

We do recognize a rotate already in GENERIC

  return x r<< 8;

But this is expanded to

        movdqa  %xmm0, %xmm1
        psrlw   $8, %xmm0
        psllw   $8, %xmm1
        por     %xmm1, %xmm0

probably the target could advertise a rotate insn for that mode, restricted to
an argument of 8?

IIRC, I didn't use vector extensions for the corresponding shift intrinsics
because for large shift amounts they set the result to 0. But for a constant
scalar, we could lower the builtin to a shift (or fold to 0).

  parent reply	other threads:[~2020-09-03 20:41 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-03 12:58 [Bug target/96918] New: " gabravier at gmail dot com
2020-09-03 13:03 ` [Bug target/96918] " rguenth at gcc dot gnu.org
2020-09-03 13:13 ` gabravier at gmail dot com
2020-09-03 13:21 ` jakub at gcc dot gnu.org
2020-09-03 14:30 ` gabravier at gmail dot com
2020-09-03 20:41 ` glisse at gcc dot gnu.org [this message]
2020-09-03 20:57 ` jakub at gcc dot gnu.org
2020-09-04  6:49 ` rguenth at gcc dot gnu.org
2021-08-03  5:10 ` pinskia at gcc dot gnu.org
2021-08-03  5:36 ` crazylht at gmail dot com
2021-08-03  5:51 ` crazylht at gmail dot com

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