[Bug rtl-optimization/97249] Missing vec_select and subreg optimization

["crazylht at gmail dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97249

--- Comment #7 from Hongtao.liu <crazylht at gmail dot com> ---
I'm testing
---
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 869f0d11b2e..9c397157f28 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -4170,6 +4170,33 @@ simplify_binary_operation_1 (enum rtx_code code,
machine_mode mode,
                    return subop1;
                }
            }
+
+         /* For cases like
+            (vec_select:V2SI (subreg:V4SI (inner:V2SI) 0)
+                             (parallel [(const_int 0) (const_int 1)])).
+            return inner directly.  */
+         if (GET_CODE (trueop0) == SUBREG
+             && paradoxical_subreg_p (trueop0)
+             && mode == GET_MODE (XEXP (trueop0, 0))
+             && (GET_MODE_NUNITS (GET_MODE (trueop0))).is_constant (&l0)
+             && (GET_MODE_NUNITS (mode)).is_constant (&l1)
+             && l0 % l1 == 0)
+           {
+             gcc_assert (known_eq (XVECLEN (trueop1, 0), l1));
+             unsigned HOST_WIDE_INT expect = (HOST_WIDE_INT_1U << l1) - 1;
+             unsigned HOST_WIDE_INT sel = 0;
+             int i = 0;
+             for (;i != l1; i++)
+               {
+                 rtx j = XVECEXP (trueop1, 0, i);
+                 if (!CONST_INT_P (j))
+                   break;
+                 sel |= HOST_WIDE_INT_1U << UINTVAL (j);
+               }
+             /* ??? Need to simplify XEXP (trueop0, 0) here.  */
+             if (sel == expect)
+               return XEXP (trueop0, 0);
+           }
        }

       if (XVECLEN (trueop1, 0) == 1
---