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From: "amonakov at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/97366] [8/9/10/11 Regression] Redundant load with SSE/AVX vector intrinsics
Date: Mon, 12 Oct 2020 11:04:00 +0000	[thread overview]
Message-ID: <bug-97366-4-Caa95mehJF@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-97366-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97366

--- Comment #5 from Alexander Monakov <amonakov at gcc dot gnu.org> ---
afaict LRA is just following IRA decisions, and IRA allocates that pseudo to
memory due to costs.

Not sure where strange cost is coming from, but it depends on x86 tuning
options: with -mtune=skylake we get the expected code, with -mtune=haswell we
get 128-bit vectors right and extra load for 256-bit, with -mtune=generic both
cases have extra loads.

  parent reply	other threads:[~2020-10-12 11:04 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-11  6:41 [Bug target/97366] New: " peter at cordes dot ca
2020-10-11  6:42 ` [Bug target/97366] " peter at cordes dot ca
2020-10-11 16:05 ` amonakov at gcc dot gnu.org
2020-10-12  6:28 ` rguenth at gcc dot gnu.org
2020-10-12  9:26 ` jakub at gcc dot gnu.org
2020-10-12 11:04 ` amonakov at gcc dot gnu.org [this message]
2020-10-12 11:43 ` rguenth at gcc dot gnu.org
2020-10-20  7:59 ` crazylht at gmail dot com
2021-02-19 20:19 ` vmakarov at gcc dot gnu.org
2021-02-19 20:20 ` vmakarov at gcc dot gnu.org
2021-05-14  9:54 ` [Bug target/97366] [9/10/11/12 " jakub at gcc dot gnu.org
2021-06-01  8:18 ` rguenth at gcc dot gnu.org
2022-05-27  9:43 ` [Bug target/97366] [10/11/12/13 " rguenth at gcc dot gnu.org
2022-06-28 10:42 ` jakub at gcc dot gnu.org
2023-07-07 10:38 ` [Bug target/97366] [11/12/13/14 " rguenth at gcc dot gnu.org

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