[Bug other/97417] RISC-V Unnecessary andi instruction when loading volatile bool

["admin at levyhsu dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417

--- Comment #39 from Levy <admin at levyhsu dot com> ---
Checked all pass from 250r.shorten_memrefs to 270r.ce2

In 269r.combine I saw the following combination merged the replaced address:
-------------------------------------------------------
modifying insn i3    27: r92:DI=r96:DI+0x300
      REG_DEAD r96:DI
deferring rescan insn with uid = 27.
(!)allowing combination of insns 27 and 6
original costs 4 + 16 = 20
replacement costs 4 + 16 = 20
modifying insn i2    27: r92:DI=r96:DI+0x300
deferring rescan insn with uid = 27.
modifying insn i3     6: r82:DI=sign_extend([r96:DI+0x320])
      REG_DEAD r96:DI
deferring rescan insn with uid = 6.
(!)allowing combination of insns 27 and 8
original costs 4 + 16 = 20
replacement costs 4 + 16 = 20
modifying insn i2    27: r92:DI=r96:DI+0x300
deferring rescan insn with uid = 27.
modifying insn i3     8: r84:DI=sign_extend([r96:DI+0x324])
      REG_DEAD r96:DI
deferring rescan insn with uid = 8.
(!)allowing combination of insns 27 and 12
original costs 4 + 16 = 20
replacement costs 4 + 16 = 20
modifying insn i2    27: r92:DI=r96:DI+0x300
deferring rescan insn with uid = 27.
modifying insn i3    12: r87:DI=sign_extend([r96:DI+0x328])
      REG_DEAD r96:DI
deferring rescan insn with uid = 12.
(!)allowing combination of insns 27 and 16
original costs 4 + 16 = 20
replacement cost 16
deferring deletion of insn with uid = 27.
modifying insn i3    16: r90:DI=sign_extend([r96:DI+0x32c])
      REG_DEAD r96:DI
deferring rescan insn with uid = 16.
allowing combination of insns 18 and 19
-------------------------------------------------------
Where in 268r.ud_dce both insns 27 are same (except for memory address):

(insn 27 26 28 2 (set (reg:DI 10 a0)
        (lo_sum:DI (reg/f:DI 85)
            (symbol_ref/f:DI ("*.LC0") [flags 0x82]  <var_decl 0x7f3546fe91b0
*.LC0>))) "array_test.c":21:5 133 {*lowdi}
     (expr_list:REG_DEAD (reg/f:DI 85)
        (expr_list:REG_EQUAL (symbol_ref/f:DI ("*.LC0") [flags 0x82]  <var_decl
0x7f3546fe91b0 *.LC0>)
            (nil))))
-------------------------------------------------------
In 270r.combine (patched):

(note 27 3 6 2 NOTE_INSN_DELETED)

and following insns 768 + 32/36/40/44 were put back as:

(insn 6 27 8 2 (set (reg:DI 82 [ MEM[(int *)array_5(D) + 800B] ])
        (sign_extend:DI (mem:SI (plus:DI (reg:DI 96)
                    (const_int 800 [0x320])) [1 MEM[(int *)array_5(D) + 800B]+0
S4 A32]))) "array_test.c":7:5 90 {extendsidi2}


(insn 8 6 10 2 (set (reg:DI 84 [ MEM[(int *)array_5(D) + 804B] ])
        (sign_extend:DI (mem:SI (plus:DI (reg:DI 96)
                    (const_int 804 [0x324])) [1 MEM[(int *)array_5(D) + 804B]+0
S4 A32]))) "array_test.c":7:5 90 {extendsidi2}


(insn 12 10 14 2 (set (reg:DI 87 [ MEM[(int *)array_5(D) + 808B] ])
        (sign_extend:DI (mem:SI (plus:DI (reg:DI 96)
                    (const_int 808 [0x328])) [1 MEM[(int *)array_5(D) + 808B]+0
S4 A32]))) "array_test.c":8:5 90 {extendsidi2}

(insn 16 14 18 2 (set (reg:DI 90 [ MEM[(int *)array_5(D) + 812B] ])
        (sign_extend:DI (mem:SI (plus:DI (reg:DI 96)
                    (const_int 812 [0x32c])) [1 MEM[(int *)array_5(D) + 812B]+0
S4 A32]))) "array_test.c":9:5 90 {extendsidi2}
     (expr_list:REG_DEAD (reg:DI 96)
        (nil)))

Maybe combine.c needs some modification?