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From: "wilson at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug other/97417] RISC-V Unnecessary andi instruction when loading
 volatile bool
Date: Tue, 27 Oct 2020 15:25:07 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D97417

--- Comment #5 from Jim Wilson <wilson at gcc dot gnu.org> ---
Yes, the volatile is the problem.  We need to disable some optimizations li=
ke
the combiner to avoid breaking the semantics of volatile.  However, if you =
try
looking at other ports, like arm, you can see that they don't have this pro=
blem
because they generate different RTL at the start and hence do not need the
combiner to generate the sign-extended load.  So the proposal here is that =
we
modify the RISC-V gcc port to also emit the sign-extended load at RTL
generation time, which solves this problem. And then we need to do some tes=
ting
to make sure that this actually generates good code in every case, as we do=
n't
want to accidentally introduce a code size or performance regression while
fixing this volatile optimization problem.

If you are curious about the combiner issue, see the init_recog_no_volatile
call in combine.c.  If you comment that out, the andi will be optimized awa=
y.=20
But we can't remove that call, because that would break programs using
volatile.=