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From: "jiawei at iscas dot ac.cn" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/97417] RISC-V Unnecessary andi instruction when loading
 volatile bool
Date: Fri, 25 Dec 2020 09:09:40 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D97417

--- Comment #59 from jiawei <jiawei at iscas dot ac.cn> ---
   Hi Kito,

   Okay, I will retest the benchmark on gem5.



   =E5=8F=91=E8=87=AA=E6=88=91=E7=9A=84=E5=B0=8F=E7=B1=B3=E6=89=8B=E6=9C=BA=
=E5=9C=A8 "kito at gcc dot gnu.org"
   <gcc-bugzilla@gcc.gnu.org>=EF=BC=8C2020=E5=B9=B412=E6=9C=8825=E6=97=A5 =
=E4=B8=8A=E5=8D=8811:31=E5=86=99=E9=81=93=EF=BC=9A

     https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D97417

     --- Comment #58 from Kito Cheng <kito at gcc dot gnu.org[1]> ---
     Hi jiawei:

     I would suggest you just using inst count rather than cycle or
     time for
     measuring benchmark if you using qemu, since qemu is functional
     simulator not
     cycle accurate neither nearly-cycle accurate simulator, so the
     performance
     number is coming from your native host (x86_64) cpu, and it also
     might
     sensitive on your host loading. or maybe you could try gem5 for
     that?

     Thanks your helping benchmark that :)

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