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Subject: [Bug target/97417] RISC-V Unnecessary andi instruction when loading
 volatile bool
Date: Sat, 13 Feb 2021 20:24:13 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D97417

--- Comment #60 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jim Wilson <wilson@gcc.gnu.org>:

https://gcc.gnu.org/g:a4953810bac524e19126a2745c75fed58db962c2

commit r11-7236-ga4953810bac524e19126a2745c75fed58db962c2
Author: Jim Wilson <jimw@sifive.com>
Date:   Sat Feb 13 12:13:08 2021 -0800

    RISC-V: Shorten memrefs improvement, partial fix 97417.

    We already have a check for riscv_shorten_memrefs in riscv_address_cost.
    This adds the same check to riscv_rtx_costs.  Making this work also
    requires a change to riscv_compressed_lw_address_p to work before reload
    by checking the offset and assuming any pseudo reg is OK.  Testing shows
    that this consistently gives small code size reductions.

            gcc/
            PR target/97417
            * config/riscv/riscv.c (riscv_compressed_lw_address_p): Drop ea=
rly
            exit when !reload_completed.  Only perform check for compressed=
 reg
            if reload_completed.
            (riscv_rtx_costs): In MEM case, when optimizing for size and
            shorten memrefs, if not compressible, then increase cost.=