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From: "kito at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug other/97417] RISC-V Unnecessary andi instruction when loading
 volatile bool
Date: Mon, 16 Nov 2020 03:24:08 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D97417

--- Comment #37 from Kito Cheng <kito at gcc dot gnu.org> ---
Maybe we could add a parameter to indicate the type of memory access,
plain_mem, zext_mem or sext_mem for pass_shorten_memrefs::get_si_mem_base_r=
eg.

e.g.
      for (int i =3D 0; i < 2; i++)
        {=20=20=20
          rtx mem =3D XEXP (pat, i);=20
          rtx addr;
          mem_access_type_t type;
          if (get_si_mem_base_reg (mem, &addr, &type))
            {=20=20=20
              HOST_WIDE_INT regno =3D REGNO (XEXP (addr, 0));
              /* Do not transform store zero as these cannot be compressed.=
  */
              if (i =3D=3D 0)
                {=20=20=20
                  if (XEXP (pat, 1) =3D=3D CONST0_RTX (GET_MODE (XEXP (pat,=
 1))))
                    continue;
                }=20=20=20
              if (m->get_or_insert (regno) > 3)
                {
                  addr
                    =3D targetm.legitimize_address (addr, addr, GET_MODE (m=
em));
                  switch (type)
                    {
                    case plain_mem:
                      XEXP (pat, i) =3D replace_equiv_address (mem, addr);
                      break;
                    case zext_mem:
                      ...
                      break;
                    case sext_mem:
                      ...
                      break;
                    }
                  df_insn_rescan (insn);
                }=20=20=20
            }=