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Subject: [Bug other/97417] RISC-V Unnecessary andi instruction when loading
 volatile bool
Date: Wed, 04 Nov 2020 07:03:03 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D97417

--- Comment #12 from Levy <admin at levyhsu dot com> ---
(In reply to Kito Cheng from comment #11)
> > Two failed cases: shorten-memrefs-5.c & shorten-memrefs-6.c
>=20
> Seems like shorten_memrefs pass didn't handle zero_extend and sign_extend
> with memory.
>=20
> You can take a look into
> riscv-shorten-memrefs.c:pass_shorten_memrefs::analyze and add logic to
> handle zero_extend and sign_extend.
>=20
>=20
> > With one instruction less, the patched one seems right and even faster =
to me. However we still need a test on sign extend and check performance
>=20
> shorten_memrefs is optimize for size, the idea is transform several load
> instructions with large immediate to a load immediate instruction and load
> instructions with small immediate, to use C-extensions instruction as
> possible.
>=20
> so the instruction count seems increased, but the code size is smaller.

Thank you cheng, I'll have a look.=