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From: "wilson at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/97417] RISC-V Unnecessary andi instruction when loading volatile bool
Date: Wed, 16 Dec 2020 02:40:42 +0000	[thread overview]
Message-ID: <bug-97417-4-pI1aLl7cOj@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-97417-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417

--- Comment #50 from Jim Wilson <wilson at gcc dot gnu.org> ---
The combine change is inconvenient.  We can't do that in stage3, and it means
we need to make sure that this doesn't break other targets.

If the combine change is a good idea, then I think you can just modify
is_just_move rather than add a new function.  Just skip over a ZERO_EXTEND or
SIGN_EXTEND before the the general_operand check.  We might need a mode check
against UNITS_PER_WORD since extending past the word size is not necessarily a
simple move.

So the problem stems from the code in combine that is willing to do a 2->2
split if neither original instruction is a simple move.  When we add a
SIGN_EXTEND or ZERO_EXTEND they aren't considered simple moves anymore.

There is still the question of why the instruction cost allows the change. 
First I noticed that riscv_address_cost has a hook to check for shorten_memrefs
but that riscv_rtx_costs isn't calling it.  It uses riscv_address_insns
instead.  So it seems like adding a shorten_memref check to the MEM case
riscv_rtx_costs might solve the problem.  But riscv_compressed_lw_address_p has
a !reload_completed check, and combine runs before reload, so that returns the
same result for both the new and old insns.  I think that reload_completed
check isn't quite right.  If we have a pseudo-reg, then we should allow that,
but if we have an offset that is clearly not compressible, then we should
reject it before reload.  So I think the reload_completed check should be moved
down to where it checks for a compressible register.  With those two changes, I
can make the testcase work without a combine change.  Though since I changed
how shorten_memrefs works we need a check to make sure this patch doens't
change code size.  I haven't tried to do that yet.

With my changes, in the combine dump, I see

Successfully matched this instruction:
(set (reg/f:DI 92)
    (plus:DI (reg:DI 96)
        (const_int 768 [0x300])))
Successfully matched this instruction:
(set (reg:DI 82 [ MEM[(intD.1 *)array_5(D) + 800B] ])
    (sign_extend:DI (mem:SI (plus:DI (reg:DI 96)
                (const_int 800 [0x320])) [1 MEM[(intD.1 *)array_5(D) + 800B]+0
S4 A32])))
rejecting combination of insns 27 and 6
original costs 4 + 16 = 20
replacement costs 4 + 20 = 24

so now the replacement gets rejected because of the increased address cost.

  parent reply	other threads:[~2020-12-16  2:40 UTC|newest]

Thread overview: 63+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-14 11:56 [Bug other/97417] New: " kjetilos at gmail dot com
2020-10-15 20:34 ` [Bug other/97417] " wilson at gcc dot gnu.org
2020-10-21  3:36 ` jiawei at iscas dot ac.cn
2020-10-21  5:58 ` wilson at gcc dot gnu.org
2020-10-27 11:18 ` jiawei at iscas dot ac.cn
2020-10-27 15:25 ` wilson at gcc dot gnu.org
2020-10-29  5:27 ` admin at levyhsu dot com
2020-10-29 22:49 ` wilson at gcc dot gnu.org
2020-10-30  8:35 ` admin at levyhsu dot com
2020-10-30 12:46 ` admin at levyhsu dot com
2020-11-04  6:10 ` admin at levyhsu dot com
2020-11-04  6:35 ` kito at gcc dot gnu.org
2020-11-04  7:03 ` admin at levyhsu dot com
2020-11-05 22:57 ` wilson at gcc dot gnu.org
2020-11-06  1:20 ` wilson at gcc dot gnu.org
2020-11-06  2:40 ` wilson at gcc dot gnu.org
2020-11-06  2:44 ` kito at gcc dot gnu.org
2020-11-06  3:35 ` wilson at gcc dot gnu.org
2020-11-06  9:46 ` admin at levyhsu dot com
2020-11-06 11:38 ` admin at levyhsu dot com
2020-11-06 20:44 ` wilson at gcc dot gnu.org
2020-11-06 21:08 ` wilson at gcc dot gnu.org
2020-11-09  8:35 ` admin at levyhsu dot com
2020-11-09  9:22 ` admin at levyhsu dot com
2020-11-10  5:20 ` admin at levyhsu dot com
2020-11-10  5:29 ` kito at gcc dot gnu.org
2020-11-10  5:34 ` admin at levyhsu dot com
2020-11-10  5:36 ` admin at levyhsu dot com
2020-11-10  6:01 ` admin at levyhsu dot com
2020-11-10 10:47 ` admin at levyhsu dot com
2020-11-11  1:21 ` wilson at gcc dot gnu.org
2020-11-11  5:43 ` admin at levyhsu dot com
2020-11-11  6:43 ` admin at levyhsu dot com
2020-11-11 19:35 ` wilson at gcc dot gnu.org
2020-11-12  1:26 ` admin at levyhsu dot com
2020-11-13  0:00 ` wilson at gcc dot gnu.org
2020-11-16  1:17 ` admin at levyhsu dot com
2020-11-16  3:24 ` kito at gcc dot gnu.org
2020-11-17 10:19 ` admin at levyhsu dot com
2020-11-18  6:09 ` admin at levyhsu dot com
2020-11-18 18:31 ` [Bug target/97417] " wilson at gcc dot gnu.org
2020-11-20  2:41 ` admin at levyhsu dot com
2020-11-20  3:32 ` wilson at gcc dot gnu.org
2020-11-23  6:17 ` admin at levyhsu dot com
2020-11-23  6:38 ` admin at levyhsu dot com
2020-11-23  7:43 ` admin at levyhsu dot com
2020-12-01  3:03 ` admin at levyhsu dot com
2020-12-08  9:22 ` admin at levyhsu dot com
2020-12-14 10:43 ` admin at levyhsu dot com
2020-12-15  9:55 ` admin at levyhsu dot com
2020-12-16  2:40 ` wilson at gcc dot gnu.org [this message]
2020-12-16  2:42 ` wilson at gcc dot gnu.org
2020-12-17 18:13 ` wilson at gcc dot gnu.org
2020-12-17 18:26 ` jiawei at iscas dot ac.cn
2020-12-21 15:08 ` jiawei at iscas dot ac.cn
2020-12-21 15:38 ` kito at gcc dot gnu.org
2020-12-21 16:09 ` jiawei at iscas dot ac.cn
2020-12-22  6:35 ` admin at levyhsu dot com
2020-12-25  3:31 ` kito at gcc dot gnu.org
2020-12-25  9:09 ` jiawei at iscas dot ac.cn
2021-02-13 20:24 ` cvs-commit at gcc dot gnu.org
2021-02-13 20:37 ` cvs-commit at gcc dot gnu.org
2021-02-13 20:48 ` wilson at gcc dot gnu.org

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