[Bug other/97417] RISC-V Unnecessary andi instruction when loading volatile bool

["jiawei at iscas dot ac.cn" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417

jiawei <jiawei at iscas dot ac.cn> changed:

           What    |Removed                     |Added
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                 CC|                            |jiawei at iscas dot ac.cn

--- Comment #2 from jiawei <jiawei at iscas dot ac.cn> ---
(In reply to Jim Wilson from comment #1)
> Comparing with the ARM port, I see that in the ARM port, the movqi pattern
> emits
> (insn 8 7 9 2 (set (reg:SI 117)
>         (zero_extend:SI (mem/v/c:QI (reg/f:SI 115) [1 active+0 S1 A8])))
> "tmp.c\
> ":7:7 -1
>      (nil))
> (insn 9 8 10 2 (set (reg:QI 116)
>         (subreg:QI (reg:SI 117) 0)) "tmp.c":7:7 -1
>      (nil))
> and then later it combines the subreg operation with the following
> zero_extend and cancels them out.
> 
> Whereas in the RISC-V port, the movqi pattern emits
> (insn 9 7 10 2 (set (reg:QI 76)
> 	(mem/v/c:QI (lo_sum:DI (reg:DI 74)
>                 (symbol_ref:DI ("active") [flags 0xc4]  <var_decl
> 0x7f9f0310312\
> 0 active>)) [1 active+0 S1 A8])) "tmp.c":7:7 -1
>      (nil))
> and then combine refuses to combine the following zero-extend with this insn
> as the memory operation is volatile.
> 
> So it seems we need to rewrite the RISC-V port to make movqi and movhi zero
> extend to si/di mode and then subreg.  That probably will require cascading
> changes to avoid code size and performance regressions.
> 
> Looks like a tractable small to medium size project, but will need to wait
> for a volunteer to work on it.

Hi Jim, My name is Jiawei Chen. I am from the PLCT Lab. I had recurrented this
bug, and want to try to help fixing this bug. What should I modify，is there any
suggestions?