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From: "admin at levyhsu dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug other/97417] RISC-V Unnecessary andi instruction when loading volatile bool
Date: Tue, 17 Nov 2020 10:19:18 +0000 [thread overview]
Message-ID: <bug-97417-4-xh4QvkQenr@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-97417-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417
--- Comment #38 from Levy <admin at levyhsu dot com> ---
Created attachment 49575
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49575&action=edit
riscv-shorten-memrefs_V1.patch
Did little bit change in get_si_mem_base_reg() and transform()
Now for the same c input array_test.c
int load1r (int *array)
{
int a = 0;
a += array[200];
a += array[201];
a += array[202];
a += array[203];
return a;
}
int main ()
{
int arr[300]= {0};
arr[200] = 15;
arr[201] = -33;
arr[202] = 7;
arr[203] = -999;
int b = load1r(arr);
printf("Result: %d\n",b);
return 0;
}
in loadlr, when put a debug_rtx(pat) after:
(unpatched)XEXP (pat, i) = replace_equiv_address (mem, addr);
or
(patched)XEXP (XEXP (pat, I), 0) = replace_equiv_address(XEXP (mem, 0), addr);
unpatched gcc will produce follwing insns:
---------------------------------------------------------
(set (reg:SI 81 [ MEM[(int *)array_5(D) + 800B] ])
(mem:SI (plus:DI (reg:DI 88)
(const_int 32 [0x20])) [1 MEM[(int *)array_5(D) + 800B]+0 S4 A32]))
(set (reg:SI 82 [ MEM[(int *)array_5(D) + 804B] ])
(mem:SI (plus:DI (reg:DI 89)
(const_int 36 [0x24])) [1 MEM[(int *)array_5(D) + 804B]+0 S4 A32]))
(set (reg:SI 84 [ MEM[(int *)array_5(D) + 808B] ])
(mem:SI (plus:DI (reg:DI 90)
(const_int 40 [0x28])) [1 MEM[(int *)array_5(D) + 808B]+0 S4 A32]))
(set (reg:SI 86 [ MEM[(int *)array_5(D) + 812B] ])
(mem:SI (plus:DI (reg:DI 91)
(const_int 44 [0x2c])) [1 MEM[(int *)array_5(D) + 812B]+0 S4 A32]))
---------------------------------------------------------
patched gcc will produce follwing insns:
---------------------------------------------------------
(set (reg:DI 82 [ MEM[(int *)array_5(D) + 800B] ])
(sign_extend:DI (mem:SI (plus:DI (reg:DI 92)
(const_int 32 [0x20])) [1 MEM[(int *)array_5(D) + 800B]+0 S4
A32])))
(set (reg:DI 84 [ MEM[(int *)array_5(D) + 804B] ])
(sign_extend:DI (mem:SI (plus:DI (reg:DI 93)
(const_int 36 [0x24])) [1 MEM[(int *)array_5(D) + 804B]+0 S4
A32])))
(set (reg:DI 87 [ MEM[(int *)array_5(D) + 808B] ])
(sign_extend:DI (mem:SI (plus:DI (reg:DI 94)
(const_int 40 [0x28])) [1 MEM[(int *)array_5(D) + 808B]+0 S4
A32])))
(set (reg:DI 90 [ MEM[(int *)array_5(D) + 812B] ])
(sign_extend:DI (mem:SI (plus:DI (reg:DI 95)
(const_int 44 [0x2c])) [1 MEM[(int *)array_5(D) + 812B]+0 S4
A32])))
---------------------------------------------------------
which the patched one looks ok for me, but the final assembly code still shows
no change (both under -Os)
Not quite sure where the problem is, I'll have a look near
array_test.c.250r.shorten_memrefs tomorrow.
Please ignore the coding style as it's just a debug patch
next prev parent reply other threads:[~2020-11-17 10:19 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-14 11:56 [Bug other/97417] New: " kjetilos at gmail dot com
2020-10-15 20:34 ` [Bug other/97417] " wilson at gcc dot gnu.org
2020-10-21 3:36 ` jiawei at iscas dot ac.cn
2020-10-21 5:58 ` wilson at gcc dot gnu.org
2020-10-27 11:18 ` jiawei at iscas dot ac.cn
2020-10-27 15:25 ` wilson at gcc dot gnu.org
2020-10-29 5:27 ` admin at levyhsu dot com
2020-10-29 22:49 ` wilson at gcc dot gnu.org
2020-10-30 8:35 ` admin at levyhsu dot com
2020-10-30 12:46 ` admin at levyhsu dot com
2020-11-04 6:10 ` admin at levyhsu dot com
2020-11-04 6:35 ` kito at gcc dot gnu.org
2020-11-04 7:03 ` admin at levyhsu dot com
2020-11-05 22:57 ` wilson at gcc dot gnu.org
2020-11-06 1:20 ` wilson at gcc dot gnu.org
2020-11-06 2:40 ` wilson at gcc dot gnu.org
2020-11-06 2:44 ` kito at gcc dot gnu.org
2020-11-06 3:35 ` wilson at gcc dot gnu.org
2020-11-06 9:46 ` admin at levyhsu dot com
2020-11-06 11:38 ` admin at levyhsu dot com
2020-11-06 20:44 ` wilson at gcc dot gnu.org
2020-11-06 21:08 ` wilson at gcc dot gnu.org
2020-11-09 8:35 ` admin at levyhsu dot com
2020-11-09 9:22 ` admin at levyhsu dot com
2020-11-10 5:20 ` admin at levyhsu dot com
2020-11-10 5:29 ` kito at gcc dot gnu.org
2020-11-10 5:34 ` admin at levyhsu dot com
2020-11-10 5:36 ` admin at levyhsu dot com
2020-11-10 6:01 ` admin at levyhsu dot com
2020-11-10 10:47 ` admin at levyhsu dot com
2020-11-11 1:21 ` wilson at gcc dot gnu.org
2020-11-11 5:43 ` admin at levyhsu dot com
2020-11-11 6:43 ` admin at levyhsu dot com
2020-11-11 19:35 ` wilson at gcc dot gnu.org
2020-11-12 1:26 ` admin at levyhsu dot com
2020-11-13 0:00 ` wilson at gcc dot gnu.org
2020-11-16 1:17 ` admin at levyhsu dot com
2020-11-16 3:24 ` kito at gcc dot gnu.org
2020-11-17 10:19 ` admin at levyhsu dot com [this message]
2020-11-18 6:09 ` admin at levyhsu dot com
2020-11-18 18:31 ` [Bug target/97417] " wilson at gcc dot gnu.org
2020-11-20 2:41 ` admin at levyhsu dot com
2020-11-20 3:32 ` wilson at gcc dot gnu.org
2020-11-23 6:17 ` admin at levyhsu dot com
2020-11-23 6:38 ` admin at levyhsu dot com
2020-11-23 7:43 ` admin at levyhsu dot com
2020-12-01 3:03 ` admin at levyhsu dot com
2020-12-08 9:22 ` admin at levyhsu dot com
2020-12-14 10:43 ` admin at levyhsu dot com
2020-12-15 9:55 ` admin at levyhsu dot com
2020-12-16 2:40 ` wilson at gcc dot gnu.org
2020-12-16 2:42 ` wilson at gcc dot gnu.org
2020-12-17 18:13 ` wilson at gcc dot gnu.org
2020-12-17 18:26 ` jiawei at iscas dot ac.cn
2020-12-21 15:08 ` jiawei at iscas dot ac.cn
2020-12-21 15:38 ` kito at gcc dot gnu.org
2020-12-21 16:09 ` jiawei at iscas dot ac.cn
2020-12-22 6:35 ` admin at levyhsu dot com
2020-12-25 3:31 ` kito at gcc dot gnu.org
2020-12-25 9:09 ` jiawei at iscas dot ac.cn
2021-02-13 20:24 ` cvs-commit at gcc dot gnu.org
2021-02-13 20:37 ` cvs-commit at gcc dot gnu.org
2021-02-13 20:48 ` wilson at gcc dot gnu.org
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