From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 39744385800B; Tue, 17 Nov 2020 10:19:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 39744385800B From: "admin at levyhsu dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug other/97417] RISC-V Unnecessary andi instruction when loading volatile bool Date: Tue, 17 Nov 2020 10:19:18 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: other X-Bugzilla-Version: 10.2.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: admin at levyhsu dot com X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: attachments.created Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Nov 2020 10:19:19 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D97417 --- Comment #38 from Levy --- Created attachment 49575 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=3D49575&action=3Dedit riscv-shorten-memrefs_V1.patch Did little bit change in get_si_mem_base_reg() and transform() Now for the same c input array_test.c int load1r (int *array) { int a =3D 0; a +=3D array[200]; a +=3D array[201]; a +=3D array[202]; a +=3D array[203]; return a; } int main () { int arr[300]=3D {0}; arr[200] =3D 15; arr[201] =3D -33; arr[202] =3D 7; arr[203] =3D -999; int b =3D load1r(arr); printf("Result: %d\n",b); return 0; } in loadlr, when put a debug_rtx(pat) after: (unpatched)XEXP (pat, i) =3D replace_equiv_address (mem, addr);=20 or=20 (patched)XEXP (XEXP (pat, I), 0) =3D replace_equiv_address(XEXP (mem, 0), a= ddr); unpatched gcc will produce follwing insns: --------------------------------------------------------- (set (reg:SI 81 [ MEM[(int *)array_5(D) + 800B] ]) (mem:SI (plus:DI (reg:DI 88) (const_int 32 [0x20])) [1 MEM[(int *)array_5(D) + 800B]+0 S4 A3= 2])) (set (reg:SI 82 [ MEM[(int *)array_5(D) + 804B] ]) (mem:SI (plus:DI (reg:DI 89) (const_int 36 [0x24])) [1 MEM[(int *)array_5(D) + 804B]+0 S4 A3= 2])) (set (reg:SI 84 [ MEM[(int *)array_5(D) + 808B] ]) (mem:SI (plus:DI (reg:DI 90) (const_int 40 [0x28])) [1 MEM[(int *)array_5(D) + 808B]+0 S4 A3= 2])) (set (reg:SI 86 [ MEM[(int *)array_5(D) + 812B] ]) (mem:SI (plus:DI (reg:DI 91) (const_int 44 [0x2c])) [1 MEM[(int *)array_5(D) + 812B]+0 S4 A3= 2])) --------------------------------------------------------- patched gcc will produce follwing insns: --------------------------------------------------------- (set (reg:DI 82 [ MEM[(int *)array_5(D) + 800B] ]) (sign_extend:DI (mem:SI (plus:DI (reg:DI 92) (const_int 32 [0x20])) [1 MEM[(int *)array_5(D) + 800B]+0 S4 A32]))) (set (reg:DI 84 [ MEM[(int *)array_5(D) + 804B] ]) (sign_extend:DI (mem:SI (plus:DI (reg:DI 93) (const_int 36 [0x24])) [1 MEM[(int *)array_5(D) + 804B]+0 S4 A32]))) (set (reg:DI 87 [ MEM[(int *)array_5(D) + 808B] ]) (sign_extend:DI (mem:SI (plus:DI (reg:DI 94) (const_int 40 [0x28])) [1 MEM[(int *)array_5(D) + 808B]+0 S4 A32]))) (set (reg:DI 90 [ MEM[(int *)array_5(D) + 812B] ]) (sign_extend:DI (mem:SI (plus:DI (reg:DI 95) (const_int 44 [0x2c])) [1 MEM[(int *)array_5(D) + 812B]+0 S4 A32]))) --------------------------------------------------------- which the patched one looks ok for me, but the final assembly code still sh= ows no change (both under -Os) Not quite sure where the problem is, I'll have a look near array_test.c.250r.shorten_memrefs tomorrow. Please ignore the coding style as it's just a debug patch=