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From: "jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/97528] [9/10/11 Regression] ICE in
 decompose_automod_address, at rtlanal.c:6298 (arm-linux-gnueabihf)
Date: Wed, 18 Nov 2020 16:12:01 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D97528

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jakub at gcc dot gnu.org

--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
We have:
(insn 7 6 9 2 (set (reg:SI 114 [ _3 ])
        (ashift:SI (reg:SI 122 [ d ])
            (const_int 1 [0x1]))) "pr97528-2.c":14:9 147 {*arm_shiftsi3}
     (expr_list:REG_DEAD (reg:SI 122 [ d ])
        (nil)))
...
(insn 12 25 24 2 (set (mem/c:V4HI (post_modify:SI (reg/v/f:SI 118 [ dst ])
                (plus:SI (reg/v/f:SI 118 [ dst ])
                    (reg:SI 114 [ _3 ]))) [0 MEM[(short int[4] *)&c]+0 S8 A=
16])
        (unspec:V4HI [
                (reg:V4HI 117 [ _14 ])
            ] UNSPEC_VST1)) "pr97528-2.c":13:5 2508 {neon_vst1v4hi}
     (expr_list:REG_INC (reg/v/f:SI 118 [ dst ])
        (nil)))
and combine attempts to propagate the shift into the insn:
(insn 12 25 24 2 (set (mem/c:V4HI (post_modify:SI (reg/v/f:SI 118 [ dst ])
                (plus:SI (mult:SI (reg:SI 122 [ d ])
                        (const_int 2 [0x2]))
                    (reg/v/f:SI 118 [ dst ]))) [0 MEM[(short int[4] *)&c]+0=
 S8
A16])
        (unspec:V4HI [
                (reg:V4HI 117 [ _14 ])
            ] UNSPEC_VST1)) "pr97528-2.c":13:5 2508 {neon_vst1v4hi}
     (expr_list:REG_INC (reg/v/f:SI 118 [ dst ])
        (nil)))
That is not valid RTL, as documented:
   Currently, the compiler can only handle second operands of the
   form (plus (reg) (reg)) and (plus (reg) (const_int)), where
   the first operand of the PLUS has to be the same register as
   the first operand of the *_MODIFY.=