[Bug target/97682] Miscompiled tail call with -fPIC

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97682

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Kito Cheng <kito@gcc.gnu.org>:

https://gcc.gnu.org/g:4ba2f918583089172ac899c8eecaddef0d47cd85

commit r10-9033-g4ba2f918583089172ac899c8eecaddef0d47cd85
Author: Monk Chiang <monk.chiang@sifive.com>
Date:   Fri Nov 13 19:35:11 2020 -0800

    PR target/97682 - Fix to reuse t1 register between call address and
epilogue.

      - When expanding the call pattern, choose t1 register be a jump register.
        Epilogue also uses a t1 register to adjust Stack point. The call
pattern
        and epilogue will initial t1 twice, if both are generated in the same
        function. The call pattern will emit 'la t1,symbol' and 'jalr
t1'instructions.
        Epilogue also emits 'li t1,4096' and 'addi sp,sp,t1' instructions.
        But li and addi instructions will be placed between la and jalr
instructions.
        The la instruction will be removed by some optimizations,
        because t1 register define twice, the first define instruction look
        likes duplicate.

      - To resolve this issue, Prologue and Epilogue use the t0 register
        be a temporary register, the call pattern use the t1 register be
        a temporary register.

    gcc/
    2020-11-13  Monk Chiang  <monk.chiang@sifive.com>

            PR target/97682
            * config/riscv/riscv.h (RISCV_PROLOGUE_TEMP_REGNUM): Change
register
            to t0.
            (RISCV_CALL_ADDRESS_TEMP_REGNUM): New Marco, define t1 register.
            (RISCV_CALL_ADDRESS_TEMP): Use it for call instructions.
            * config/riscv/riscv.c (riscv_legitimize_call_address): Use
            RISCV_CALL_ADDRESS_TEMP.
            (riscv_compute_frame_info): Change temporary register to t0 form
t1.
            (riscv_trampoline_init): Adjust comment.

    gcc/testsuite/
    2020-11-13  Monk Chiang  <monk.chiang@sifive.com>

            PR target/97682
            * g++.target/riscv/pr97682.C: New test.
            * gcc.target/riscv/interrupt-3.c: Check register for t0.
            * gcc.target/riscv/interrupt-4.c: Likewise.

    (cherry picked from commit 207de83922bda8707aa33d6a2185e691116377e7)