From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id CF1A5398796E; Wed, 4 Nov 2020 20:07:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CF1A5398796E From: "qinzhao at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/97715] [11 Regression] ICE in insn_default_length, at config/i386/i386.md:15325 since r11-4578-gd10f3e900b0377b4 Date: Wed, 04 Nov 2020 20:07:24 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 11.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: qinzhao at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: qinzhao at gcc dot gnu.org X-Bugzilla-Target-Milestone: 11.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Nov 2020 20:07:24 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D97715 --- Comment #22 from qinzhao at gcc dot gnu.org --- proposed patch: This change fixes a bug in the i386 backend when adding -fzero-call-used-regs=3Dall on a target that has no x87 registers. When there is no x87 registers available, we should not zero stack registers. gcc/Changelog: PR target/97715 * config/i386/i386.c (zero_all_st_registers): Return earlier when the FPU is disabled. gcc/testsuite/ChnageLog: PR target/97715 * gcc.target/i386/zero-scratch-regs-32.c: New test. --- gcc/config/i386/i386.c | 5 +++++ gcc/testsuite/gcc.target/i386/zero-scratch-regs-32.c | 11 +++++++++++ 2 files changed, 16 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/zero-scratch-regs-32.c diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 6fc6228a26e..789ef727cf8 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -3640,6 +3640,11 @@ zero_all_vector_registers (HARD_REG_SET need_zeroed_hardregs) static bool zero_all_st_registers (HARD_REG_SET need_zeroed_hardregs) { + + /* If the FPU is disabled, no need to zero all st registers. */ + if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387)) + return false; + unsigned int num_of_st =3D 0; for (unsigned int regno =3D 0; regno < FIRST_PSEUDO_REGISTER; regno++) if ((STACK_REGNO_P (regno) || MMX_REGNO_P (regno)) diff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-32.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-32.c new file mode 100644 index 00000000000..ca3261fe5ea --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-32.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target *-*-linux* } } */ +/* { dg-options "-O2 -fzero-call-used-regs=3Dall -mno-80387" } */ + +int +foo (int x) +{ + return (x + 1); +} + +/* { dg-final { scan-assembler-not "fldz" } } */ + --=