From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 4AEEF3857027; Fri, 6 Nov 2020 21:07:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4AEEF3857027 From: "wilson at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/97747] New: missed combine opt with logical ops after zero extended load Date: Fri, 06 Nov 2020 21:07:21 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 10.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: wilson at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status bug_severity priority component assigned_to reporter target_milestone Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Nov 2020 21:07:21 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D97747 Bug ID: 97747 Summary: missed combine opt with logical ops after zero extended load Product: gcc Version: 10.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: wilson at gcc dot gnu.org Target Milestone: --- Consider this testcase struct { unsigned int a : 1; unsigned int b : 1; unsigned int c : 1; unsigned int d : 1; unsigned int pad1 : 28; } s; void sub (void) { s.a =3D 1; s.c =3D 1; } Compiling with -O2 -S for ARM I get sub: @ args =3D 0, pretend =3D 0, frame =3D 0 @ frame_needed =3D 0, uses_anonymous_args =3D 0 @ link register save eliminated. movw r2, #:lower16:.LANCHOR0 movt r2, #:upper16:.LANCHOR0 ldrb r3, [r2] @ zero_extendqisi2 bic r3, r3, #5 orr r3, r3, #5 strb r3, [r2] bx lr The bic bit-clear instruction is obviously unnecessary. In the combine dump file I see that we have (insn 9 7 11 2 (set (reg:SI 120) (and:SI (reg:SI 119 [ MEM [(struct *)&sD.5619] ]) (const_int -6 [0xfffffffffffffffa]))) "tmp.c":13:7 90 {*arm_andsi3_insn} (expr_list:REG_DEAD (reg:SI 119 [ MEM [(struct=20 *)&sD.5619] ]) (nil))) (insn 11 9 13 2 (set (reg:SI 122) (ior:SI (reg:SI 120) (const_int 5 [0x5]))) "tmp.c":13:7 106 {*iorsi3_insn} (expr_list:REG_DEAD (reg:SI 120) (nil))) And the combiner does: Trying 9 -> 11: 9: r120:SI=3Dr119:SI&0xfffffffffffffffa REG_DEAD r119:SI 11: r122:SI=3Dr120:SI|0x5 REG_DEAD r120:SI Failed to match this instruction: (set (reg:SI 122) (ior:SI (and:SI (reg:SI 119 [ MEM [(struct *)&sD.5619]= ]) (const_int 250 [0xfa])) (const_int 5 [0x5]))) The problem here is that the ARM port generated a zero_extend for the load byte, so combine knows that r120 has only 8 nonzero bits, it modified the -= 6 to 250 and then fails to notice that the and operation can be folded away beca= use in SImode the operation is no longer redundant with the modified constant. On targets that do not generate the zero_extend, the and -6 operation gets optimized away in combine. For instance, with the current RISC-V port I get sub: lui a4,%hi(s) lbu a5,%lo(s)(a4) ori a5,a5,5 sb a5,%lo(s)(a4) ret This likely fails on any target where movqi generates a zero extended load.=