[Bug rtl-optimization/97756] New: Inefficient handling of 128-bit arguments

["tkoenig at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97756

            Bug ID: 97756
           Summary: Inefficient handling of 128-bit arguments
           Product: gcc
           Version: 11.0
            Status: UNCONFIRMED
          Severity: enhancement
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: tkoenig at gcc dot gnu.org
  Target Milestone: ---

This is an offshoot from PR 97459.

The code

#define ONE ((__uint128_t) 1)
#define TWO_64 (ONE << 64)
#define MASK60 ((1ul << 60) - 1)

typedef __uint128_t mytype;

void
div_rem_13_v2 (mytype n, mytype *div, unsigned int *rem)
{
  const mytype magic = TWO_64 * 14189803133622732012u + 5675921253449092805u *
ONE;
  unsigned long a, b, c;
  unsigned int r;

  a = n & MASK60;
  b = (n >> 60);
  b = b & MASK60;
  c = (n >> 120);
  r = (a+b+c) % 13;
  n = n - r;
  *div = n * magic;
  *rem = r;
}

when compiled on x86_64 on Zen with -O3 -march=native has quite
some register shuffling at the beginning:

   0:   49 89 f0                mov    %rsi,%r8
   3:   48 89 fe                mov    %rdi,%rsi
   6:   49 89 d1                mov    %rdx,%r9
   9:   48 ba ff ff ff ff ff    movabs $0xfffffffffffffff,%rdx
  10:   ff ff 0f 
  13:   4c 89 c7                mov    %r8,%rdi
  16:   48 89 f0                mov    %rsi,%rax
  19:   49 89 c8                mov    %rcx,%r8
  1c:   48 89 f1                mov    %rsi,%rcx
  1f:   49 89 fa                mov    %rdi,%r10
  22:   48 0f ac f8 3c          shrd   $0x3c,%rdi,%rax
  27:   48 21 d1                and    %rdx,%rcx
  2a:   41 56                   push   %r14
  2c:   49 c1 ea 38             shr    $0x38,%r10
  30:   48 21 d0                and    %rdx,%rax
  33:   53                      push   %rbx
  34:   48 bb c5 4e ec c4 4e    movabs $0x4ec4ec4ec4ec4ec5,%rbx
  3b:   ec c4 4e 
  3e:   4c 01 d1                add    %r10,%rcx
  41:   45 31 db                xor    %r11d,%r11d
  44:   48 01 c1                add    %rax,%rcx
  47:   48 89 c8                mov    %rcx,%rax
  4a:   48 f7 e3                mul    %rbx
  4d:   48 c1 ea 02             shr    $0x2,%rdx
  51:   48 8d 04 52             lea    (%rdx,%rdx,2),%rax
  55:   48 8d 04 82             lea    (%rdx,%rax,4),%rax
  59:   48 89 ca                mov    %rcx,%rdx
  5c:   48 b9 ec c4 4e ec c4    movabs $0xc4ec4ec4ec4ec4ec,%rcx
  63:   4e ec c4 
  66:   48 29 c2                sub    %rax,%rdx
  69:   48 29 d6                sub    %rdx,%rsi
  6c:   49 89 d6                mov    %rdx,%r14
  6f:   4c 19 df                sbb    %r11,%rdi
  72:   48 0f af ce             imul   %rsi,%rcx
  76:   48 89 f2                mov    %rsi,%rdx
  79:   48 89 f8                mov    %rdi,%rax
  7c:   c4 e2 cb f6 fb          mulx   %rbx,%rsi,%rdi
  81:   48 0f af c3             imul   %rbx,%rax
  85:   49 89 31                mov    %rsi,(%r9)
  88:   48 01 c8                add    %rcx,%rax
  8b:   48 01 c7                add    %rax,%rdi
  8e:   49 89 79 08             mov    %rdi,0x8(%r9)
  92:   45 89 30                mov    %r14d,(%r8)
  95:   5b                      pop    %rbx
  96:   41 5e                   pop    %r14
  98:   c3                      retq