[Bug target/98214] New: SVE: Wrong code with -O3 -msve-vector-bits=512

[Bug target/98214] New: SVE: Wrong code with -O3 -msve-vector-bits=512

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98214

            Bug ID: 98214
           Summary: SVE: Wrong code with -O3 -msve-vector-bits=512
           Product: gcc
           Version: 11.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: acoplan at gcc dot gnu.org
  Target Milestone: ---

AArch64 GCC miscompiles the following testcase:

long c;
int a;
int e[14];
short b[14];
void d(long *f, long h) { *f ^= h + *f; }
int main() {
  e[2] = 1;
  for (int g = 0; g < 13; g++)
    a = b[g] = e[g];
  d(&c, a);
  for (int g = 0; g < 4; g++)
    d(&c, b[2]);
  if (c != 15)
    __builtin_abort();
}

at -O3 -march=armv8.2-a+sve -msve-vector-bits=512. Looking at the generated
code, it looks like we unconditionally call abort:

main:
        adrp    x0, .LANCHOR0
        add     x0, x0, :lo12:.LANCHOR0
        stp     x29, x30, [sp, -16]!
        mov     w2, 1
        add     x1, x0, 56
        ptrue   p0.b, vl64
        mov     x29, sp
        ldr     q0, [x0, 32]
        str     w2, [x0, 8]
        ldrsh   w2, [x0, 48]
        strh    w2, [x0, 80]
        ld1w    z1.d, p0/z, [x0]
        xtn     v0.4h, v0.4s
        st1h    z1.d, p0, [x1]
        str     w2, [x0, 84]
        str     xzr, [x0, 88]
        str     d0, [x0, 72]
        bl      abort

Possibly related to PR98196.

[Bug target/98214] [10/11 Regression] SVE: Wrong code with -O3 -msve-vector-bits=512

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98214

Alex Coplan <acoplan at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |10.3
            Summary|SVE: Wrong code with -O3    |[10/11 Regression] SVE:
                   |-msve-vector-bits=512       |Wrong code with -O3
                   |                            |-msve-vector-bits=512

--- Comment #1 from Alex Coplan <acoplan at gcc dot gnu.org> ---
Started with r10-4752-g2d56600c8de397d09a16dedd33d310a763a832ae

[Bug target/98214] [10/11 Regression] SVE: Wrong code with -O3 -msve-vector-bits=512

[rsandifo at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98214

rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at gcc dot gnu.org      |rsandifo at gcc dot gnu.org
   Last reconfirmed|                            |2020-12-30
             Status|UNCONFIRMED                 |ASSIGNED
     Ever confirmed|0                           |1

--- Comment #2 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> ---
Things go wrong in combine, because -msve-vector-bits=N
doesn't update GET_MODE_MASK properly.  Testing a patch.

[Bug target/98214] [10/11 Regression] SVE: Wrong code with -O3 -msve-vector-bits=512

[rsandifo at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98214

--- Comment #3 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> ---
*** Bug 98248 has been marked as a duplicate of this bug. ***

[Bug target/98214] [10/11 Regression] SVE: Wrong code with -O3 -msve-vector-bits=512

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98214

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Richard Sandiford <rsandifo@gcc.gnu.org>:

https://gcc.gnu.org/g:0411210fddbd3ec27c8dc1183f40f662712a2232

commit r11-6379-g0411210fddbd3ec27c8dc1183f40f662712a2232
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Thu Dec 31 16:10:47 2020 +0000

    genmodes: Update GET_MODE_MASK when changing NUNITS [PR98214]

    The static GET_MODE_MASKs for SVE vectors are based on the
    static precisions, which in turn are based on 128-bit SVE.
    The precisions are later updated based on -msve-vector-bits
    (usually to become variable length), but the GET_MODE_MASK
    stayed the same.  This caused combine to fold:

      (*_extract:DI (subreg:DI (reg:VNxMM R) 0) ...)

    to zero because the extracted bits appeared to be insignificant.

    gcc/
            PR rtl-optimization/98214
            * genmodes.c (emit_insn_modes_h): Emit a definition of
CONST_MODE_MASK.
            (emit_mode_mask): Treat mode_mask_array as non-constant if
adj_nunits.
            (emit_mode_adjustments): Update GET_MODE_MASK when updating
            GET_MODE_NUNITS.
            * machmode.h (mode_mask_array): Use CONST_MODE_MASK.

[Bug target/98214] [10 Regression] SVE: Wrong code with -O3 -msve-vector-bits=512

[rsandifo at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98214

rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[10/11 Regression] SVE:     |[10 Regression] SVE: Wrong
                   |Wrong code with -O3         |code with -O3
                   |-msve-vector-bits=512       |-msve-vector-bits=512

--- Comment #5 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> ---
Fixed on trunk so far.

[Bug target/98214] [10 Regression] SVE: Wrong code with -O3 -msve-vector-bits=512

[rsandifo at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98214

rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|ASSIGNED                    |RESOLVED

--- Comment #6 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> ---
Fixed for GCC 10 by r10-9258.

[Bug target/98214] [10 Regression] SVE: Wrong code with -O3 -msve-vector-bits=512

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98214

--- Comment #7 from ktkachov at gcc dot gnu.org ---
*** Bug 98196 has been marked as a duplicate of this bug. ***