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From: "ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/98218] [TARGET_MMX_WITH_SSE] Implement 64bit vector
 compares (AVX512 masked compares missing)
Date: Wed, 12 May 2021 18:57:03 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D98218

--- Comment #13 from Uro=C5=A1 Bizjak <ubizjak at gmail dot com> ---
(In reply to Uro=C5=A1 Bizjak from comment #12)
> Yeah, this is a non-existent SSE "cmove". I tried to find all paths where
> this should divert to a sequence of logic instructions or PBLENDB, but due
> to plethora of ISAs some cmove expansions fell through the cracks.
> Fortunately, easy to fix problem, please just provide a testcase.

A wild guess: you are compiling for TARGET_XOP?

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index d433c524652..7fc2e5d781c 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1816,11 +1816,11 @@

 ;; XOP parallel XMM conditional moves
 (define_insn "*xop_pcmov_<mode>"
-  [(set (match_operand:MMXMODEI 0 "register_operand" "=3Dx")
-        (if_then_else:MMXMODEI
-          (match_operand:MMXMODEI 3 "register_operand" "x")
-          (match_operand:MMXMODEI 1 "register_operand" "x")
-          (match_operand:MMXMODEI 2 "register_operand" "x")))]
+  [(set (match_operand:MMXMODE124 0 "register_operand" "=3Dx")
+        (if_then_else:MMXMODE124
+          (match_operand:MMXMODE124 3 "register_operand" "x")
+          (match_operand:MMXMODE124 1 "register_operand" "x")
+          (match_operand:MMXMODE124 2 "register_operand" "x")))]
   "TARGET_XOP && TARGET_MMX_WITH_SSE"
   "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "sse4arg")])=