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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/98477] aarch64: Unnecessary GPR -> FPR moves for
 conditional select
Date: Wed, 24 Apr 2024 00:02:26 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D98477

--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
So adding the `r` alternative to *cmov<mode>_insn (GPF) works kinda of but =
then
we seem to have a register allocation issue.

Even this still causes FPREGS from being chosen:
```
void
foo (int a, double *b)
{
  double t =3D a ? 10000.0 : 200.0;
  asm("":"+r"(t));
  *b =3D t;
}

```

Someone else will need to look into register allocator issue later on.

I did find a testcase where we don't get the fmovs though (which forces to =
use
x0).
```
void
foo (int a, double *b)
{
  double t =3D a ? 10000.0 : 200.0;
  register double tt __asm__("x0");
  tt =3D t;
  asm("":"+r"(tt));
  *b =3D tt;
}

```

With that we now get:
```
        cmp     w0, 0
        mov     x0, 149533581377536
        mov     x2, 4641240890982006784
        movk    x0, 0x40c3, lsl 48
        csel    x0, x2, x0, eq
        str     x0, [x1]
        ret
```

So at least I can write up a testcase ...=