[Bug middle-end/98689] [11 Regression] FAIL: gcc.dg/torture/stackalign/builtin-return-1.c -O1 execution test

["danglin at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98689

John David Anglin <danglin at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |rsandifo at sources dot redhat.com
          Component|other                       |middle-end

--- Comment #2 from John David Anglin <danglin at gcc dot gnu.org> ---
Introduced by the following commit:

commit 0b76990a9d75d97b84014e37519086b81824c307 (HEAD)
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Thu Dec 17 00:15:12 2020 +0000

    fwprop: Rewrite to use RTL SSA

    This patch rewrites fwprop.c to use the RTL SSA framework.  It tries
    as far as possible to mimic the old behaviour, even in caes where
    that doesn't fit naturally with the new framework.  I've added ???
    comments to mark those places, but I think <E2><80><9C>fixing<E2><80><9D>
them should
    be done separately to make bisection easier.

    In particular:

    * The old implementation iterated over uses, and after a successful
      substitution, the new insn's uses were added to the end of the list.
      The pass still processed those uses, but because it processed them at
      the end, it didn't fully optimise one instruction before propagating
      it into the next.

      The new version follows the same approach for comparison purposes,
      but I'd like to drop that as a follow-on patch.

    * The old implementation operated on single use sites (DF_REF_LOCs).
      This doesn't work well for instructions with match_dups, where it's
      necessary to update both an operand and its dups at the same time.
      For example, attempting to substitute into a divmod instruction would
      fail because only the div or the mod side would be updated.

      The new version again follows this to some extent for comparison
      purposes (although not exactly).  Again I'd like to drop it as a
      follow-on patch.

      One difference is that if a register occurs in multiple MEM addresses
      in a set, the new version will try to update them all at once.  This is
      what causes the SVE ACLE st4* output to improve.

    Also, the old version didn't naturally guarantee termination (PR79405),
    whereas the new one does.

    gcc/
            * fwprop.c: Rewrite to use the RTL SSA framework.

    gcc/testsuite/
            * gcc.dg/rtl/x86_64/test-return-const.c.before-fwprop.c: Don't
            expect insn updates to be deferred.
            * gcc.target/aarch64/sve/acle/asm/st4_s8.c: Expect the addition
            to be folded into the address.
            * gcc.target/aarch64/sve/acle/asm/st4_u8.c: Likewise.