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From: "clyon at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/98849] [11 Regression] ICE in expand_shift_1, at
 expmed.c:2658 since g:7432f255b70811dafaf325d9403
Date: Wed, 27 Jan 2021 13:38:01 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D98849

--- Comment #6 from Christophe Lyon <clyon at gcc dot gnu.org> ---
I'm not familiar with iwmmxt, but the testcase in comment #2 is vectorized
with:
* -mcpu=3Dcortex-a9 -mfpu=3Dauto -mfloat-abi=3Dhard (uses Neon FPU)
* -mcpu=3Dcortex-m55 -mfpu=3Dauto -mfloat-abi=3Dhard (uses MVE/Helium FPU)
in both cases -mfloat-abi=3Dhard is required.

Using -mcpu=3Diwmmxt -mfpu=3Dauto -mfloat-abi=3Dhard fails because:
cc1: error: '-mfloat-abi=3Dhard': selected processor lacks an FPU

so to answer your question arm does have vector shift by scalar.

But the Neon/MVE patterns use a const_vector constraint (see
mve_vshlq_<supf><mode> and vashl<mode>3 in vec-common.md and ashl<mode>3_iw=
mmxt
in iwmmxt.md)=