* [Bug target/98853] [11 Regression] wrong use of bfxil at -O1
2021-01-27 12:29 [Bug target/98853] New: [11 Regression] wrong use of bfxil at -O1 zsojka at seznam dot cz
@ 2021-01-27 13:13 ` rguenth at gcc dot gnu.org
2021-01-27 14:16 ` jakub at gcc dot gnu.org
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From: rguenth at gcc dot gnu.org @ 2021-01-27 13:13 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98853
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Target Milestone|--- |11.0
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2021-01-27 13:13 ` [Bug target/98853] " rguenth at gcc dot gnu.org
@ 2021-01-27 14:16 ` jakub at gcc dot gnu.org
2021-01-27 14:25 ` [Bug target/98853] [9/10/11 " jakub at gcc dot gnu.org
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From: jakub at gcc dot gnu.org @ 2021-01-27 14:16 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98853
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |jakub at gcc dot gnu.org
--- Comment #1 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
I admit I know next to nothing about AArch64, but the
https://gcc.gnu.org/legacy-ml/gcc-patches/2018-07/msg01895.html
patch certainly doesn't emit what it claims to, and from a brief look at the
assembler guide it appears that emitting what the patch claims to shall fix it.
So I think this should be:
--- gcc/config/aarch64/aarch64.md.jj 2021-01-04 10:25:46.435147744 +0100
+++ gcc/config/aarch64/aarch64.md 2021-01-27 15:13:13.993275204 +0100
@@ -5724,10 +5724,10 @@ (define_insn "*aarch64_bfxilsi_uxtw"
{
case 0:
operands[3] = GEN_INT (ctz_hwi (~INTVAL (operands[3])));
- return "bfxil\\t%0, %1, 0, %3";
+ return "bfxil\\t%w0, %w1, 0, %3";
case 1:
operands[3] = GEN_INT (ctz_hwi (~INTVAL (operands[4])));
- return "bfxil\\t%0, %2, 0, %3";
+ return "bfxil\\t%w0, %w2, 0, %3";
default:
gcc_unreachable ();
}
^ permalink raw reply [flat|nested] 11+ messages in thread* [Bug target/98853] [9/10/11 Regression] wrong use of bfxil at -O1
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2021-01-27 13:13 ` [Bug target/98853] " rguenth at gcc dot gnu.org
2021-01-27 14:16 ` jakub at gcc dot gnu.org
@ 2021-01-27 14:25 ` jakub at gcc dot gnu.org
2021-01-27 14:31 ` jakub at gcc dot gnu.org
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From: jakub at gcc dot gnu.org @ 2021-01-27 14:25 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98853
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Target Milestone|11.0 |9.4
Assignee|unassigned at gcc dot gnu.org |jakub at gcc dot gnu.org
Summary|[11 Regression] wrong use |[9/10/11 Regression] wrong
|of bfxil at -O1 |use of bfxil at -O1
--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
That change has been introduced in
r9-2905-g2dc09f66b3b49d821e4bd68d3c97ff51d5e080d4 , so I think we have at least
latent wrong-code in 9 and 10 too.
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From: jakub at gcc dot gnu.org @ 2021-01-27 14:31 UTC (permalink / raw)
To: gcc-bugs
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--- Comment #3 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Created attachment 50069
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=50069&action=edit
gcc11-pr98853.patch
Untested fix.
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From: cvs-commit at gcc dot gnu.org @ 2021-01-27 19:36 UTC (permalink / raw)
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--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:
https://gcc.gnu.org/g:55163419211c6f17e3e22c68304384eba35782a3
commit r11-6941-g55163419211c6f17e3e22c68304384eba35782a3
Author: Jakub Jelinek <jakub@redhat.com>
Date: Wed Jan 27 20:35:21 2021 +0100
aarch64: Fix up *aarch64_bfxilsi_uxtw [PR98853]
The https://gcc.gnu.org/legacy-ml/gcc-patches/2018-07/msg01895.html
patch that introduced this pattern claimed:
Would generate:
combine_balanced_int:
bfxil w0, w1, 0, 16
uxtw x0, w0
ret
But with this patch generates:
combine_balanced_int:
bfxil w0, w1, 0, 16
ret
and it is indeed what it should generate, but it doesn't do that,
it emits bfxil x0, x1, 0, 16
instead which doesn't zero extend from 32 to 64 bits, but preserves
the bits from the destination register.
2021-01-27 Jakub Jelinek <jakub@redhat.com>
PR target/98853
* config/aarch64/aarch64.md (*aarch64_bfxilsi_uxtw): Use
%w0, %w1 and %2 instead of %0, %1 and %2.
* gcc.c-torture/execute/pr98853-1.c: New test.
* gcc.c-torture/execute/pr98853-2.c: New test.
^ permalink raw reply [flat|nested] 11+ messages in thread* [Bug target/98853] [9/10 Regression] wrong use of bfxil at -O1
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@ 2021-01-27 19:39 ` jakub at gcc dot gnu.org
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From: jakub at gcc dot gnu.org @ 2021-01-27 19:39 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98853
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Last reconfirmed| |2021-01-27
Summary|[9/10/11 Regression] wrong |[9/10 Regression] wrong use
|use of bfxil at -O1 |of bfxil at -O1
Status|UNCONFIRMED |ASSIGNED
Ever confirmed|0 |1
--- Comment #5 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Fixed on the trunk so far.
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2021-01-27 19:39 ` [Bug target/98853] [9/10 " jakub at gcc dot gnu.org
@ 2021-01-29 19:20 ` cvs-commit at gcc dot gnu.org
2021-01-29 19:24 ` [Bug target/98853] [9 " jakub at gcc dot gnu.org
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From: cvs-commit at gcc dot gnu.org @ 2021-01-29 19:20 UTC (permalink / raw)
To: gcc-bugs
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--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Jakub Jelinek
<jakub@gcc.gnu.org>:
https://gcc.gnu.org/g:2a2c1e22c2501457608f12d5ab560caaca59c425
commit r10-9322-g2a2c1e22c2501457608f12d5ab560caaca59c425
Author: Jakub Jelinek <jakub@redhat.com>
Date: Wed Jan 27 20:35:21 2021 +0100
aarch64: Fix up *aarch64_bfxilsi_uxtw [PR98853]
The https://gcc.gnu.org/legacy-ml/gcc-patches/2018-07/msg01895.html
patch that introduced this pattern claimed:
Would generate:
combine_balanced_int:
bfxil w0, w1, 0, 16
uxtw x0, w0
ret
But with this patch generates:
combine_balanced_int:
bfxil w0, w1, 0, 16
ret
and it is indeed what it should generate, but it doesn't do that,
it emits bfxil x0, x1, 0, 16
instead which doesn't zero extend from 32 to 64 bits, but preserves
the bits from the destination register.
2021-01-27 Jakub Jelinek <jakub@redhat.com>
PR target/98853
* config/aarch64/aarch64.md (*aarch64_bfxilsi_uxtw): Use
%w0, %w1 and %2 instead of %0, %1 and %2.
* gcc.c-torture/execute/pr98853-1.c: New test.
* gcc.c-torture/execute/pr98853-2.c: New test.
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@ 2021-01-29 19:24 ` jakub at gcc dot gnu.org
2021-04-20 23:31 ` cvs-commit at gcc dot gnu.org
2021-04-22 13:32 ` jakub at gcc dot gnu.org
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From: jakub at gcc dot gnu.org @ 2021-01-29 19:24 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98853
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Summary|[9/10 Regression] wrong use |[9 Regression] wrong use of
|of bfxil at -O1 |bfxil at -O1
--- Comment #7 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Fixed for 10.3+ too.
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2021-01-29 19:24 ` [Bug target/98853] [9 " jakub at gcc dot gnu.org
@ 2021-04-20 23:31 ` cvs-commit at gcc dot gnu.org
2021-04-22 13:32 ` jakub at gcc dot gnu.org
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From: cvs-commit at gcc dot gnu.org @ 2021-04-20 23:31 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98853
--- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Jakub Jelinek
<jakub@gcc.gnu.org>:
https://gcc.gnu.org/g:bde3846fb90f51b75685c9b6d677015daaec5f69
commit r9-9411-gbde3846fb90f51b75685c9b6d677015daaec5f69
Author: Jakub Jelinek <jakub@redhat.com>
Date: Wed Jan 27 20:35:21 2021 +0100
aarch64: Fix up *aarch64_bfxilsi_uxtw [PR98853]
The https://gcc.gnu.org/legacy-ml/gcc-patches/2018-07/msg01895.html
patch that introduced this pattern claimed:
Would generate:
combine_balanced_int:
bfxil w0, w1, 0, 16
uxtw x0, w0
ret
But with this patch generates:
combine_balanced_int:
bfxil w0, w1, 0, 16
ret
and it is indeed what it should generate, but it doesn't do that,
it emits bfxil x0, x1, 0, 16
instead which doesn't zero extend from 32 to 64 bits, but preserves
the bits from the destination register.
2021-01-27 Jakub Jelinek <jakub@redhat.com>
PR target/98853
* config/aarch64/aarch64.md (*aarch64_bfxilsi_uxtw): Use
%w0, %w1 and %2 instead of %0, %1 and %2.
* gcc.c-torture/execute/pr98853-1.c: New test.
* gcc.c-torture/execute/pr98853-2.c: New test.
(cherry picked from commit 2a2c1e22c2501457608f12d5ab560caaca59c425)
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From: jakub at gcc dot gnu.org @ 2021-04-22 13:32 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98853
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Status|ASSIGNED |RESOLVED
--- Comment #9 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Fixed.
^ permalink raw reply [flat|nested] 11+ messages in thread